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    Conversion employing delta-sigma modulation
    2.
    发明公开
    Conversion employing delta-sigma modulation 有权
    Wandlungsystem mit Delta-Sigma-Modulation

    公开(公告)号：EP1487111A1

    公开(公告)日：2004-12-15

    申请号：EP03025703.4

    申请日：2003-11-07

    申请人： Northrop Grumman Corporation

    发明人： Robinson, Ian Stuart ,  Hinrichs, Jeffrey M. ,  Weber, Kenneth B. ,  Patel, Jasmine Upendra ,  MacFalda, Paul Charles ,  Skones, William Marvin

    IPC分类号： H03M3/02

    CPC分类号： H03M3/50

    摘要： Signal conversion of an input signal can be achieved by processing portions of the signal through plural parallel paths, which collectively approximate a desired infinite impulse response (IIR) filter, either alone or implemented with other signal processing functions. In one aspect, each of the paths can perform filtering, noise-shaping and/or quantization on a respective portion of the input signal to provide a corresponding representation of the respective portion of the input signal, for example, a coarser representation at a higher data rate. The corresponding representations from the parallel paths can be aggregated and further processed in a desired manner, such as conversion to an analog signal.

    摘要翻译： 输入信号的信号转换可以通过多个并行路径来处理信号的部分来实现，这些并行路径共同接近期望的无限脉冲响应（IIR）滤波器，或者用其他信号处理功能实现。 在一个方面，每个路径可以在输入信号的相应部分上执行滤波，噪声整形和/或量化，以提供输入信号的相应部分的相应表示，例如较高的较大的表示 数据速率。 来自并行路径的相应表示可以以期望的方式聚合并进一步处理，例如转换为模拟信号。

    Continuous time delta-sigma modulator
    5.
    发明公开
    Continuous time delta-sigma modulator 有权
    Zeitkontinuierlicher Delta-Sigma调制器

    公开(公告)号：EP1760890A1

    公开(公告)日：2007-03-07

    申请号：EP06025838.1

    申请日：2001-06-12

    申请人： Northrop Grumman Corporation

    发明人： Oyama, Bert K. ,  Skones, William Marvin

    IPC分类号： H03M3/02

    CPC分类号： H03M3/444 ,  H03M3/402 ,  H03M3/43

    摘要： An analog-to-digital converter (170) that employs delta-sigma technology, and has particular use in a receiver for a wireless telecommunications system. The converter (170) includes a delta-sigma modulator (172), having a summing junction (180) that receives the analog input signal to be converted. A feedback from the output of a comparator (186) is subtracted from the analog input signal to generate a difference signal that is then filtered, amplified and applied to the comparator (186) for digital conversion. A sample and hold circuit (184) receives the difference signal and holds the signal for a predetermined period of time so that the input to the comparator (186) is stable. A differential limiting amplifier (188) is employed to make the high data rate output of the comparator (186) stable. The differential limiting amplifier (188) can be within the comparator (186) itself, or in the feedback path. In one embodiment, the differential amplifier (188) employs a Schottky diode clamp (226).

    摘要翻译： 一种使用delta-sigma技术的模数转换器（170），并且在用于无线电信系统的接收机中具有特别的用途。 转换器（170）包括具有接收要转换的模拟输入信号的求和结（180）的Δ-Σ调制器（172）。 从模拟输入信号中减去来自比较器（186）的输出的反馈信号，以生成差分信号，然后对其进行滤波，放大并施加到比较器（186）进行数字转换。 采样和保持电路（184）接收差分信号并将信号保持预定的时间段，使得对比较器（186）的输入是稳定的。 采用差分限幅放大器（188）使比较器（186）的高数据速率输出稳定。 差分限幅放大器（188）可以在比较器（186）本身内或反馈路径中。 在一个实施例中，差分放大器（188）采用肖特基二极管钳位（226）。

    Switching DAC pulse encoding circuit
    6.
    发明公开
    Switching DAC pulse encoding circuit 有权
    D / A-Schaltungsanordnung mit Pulskodiersystem

    公开(公告)号：EP1453206A1

    公开(公告)日：2004-09-01

    申请号：EP03026827.0

    申请日：2003-11-20

    申请人： NORTHROP GRUMMAN CORPORATION

    发明人： Skones, William Marvin ,  Nelson, Steve R.

    IPC分类号： H03M1/08

    CPC分类号： H03M3/502 ,  H03M1/0624 ,  H03M1/0872 ,  H03M1/742

    摘要： A DAC including a first switch and a second switch. The first switch receives a digital signal to be converted, and the second switch receives the digital signal delayed by one-half of a clock signal. A third switch receives a current signal from a current source and the clock signal. The third switch alternately switches the current signal to the first and second switches so that when the clock signal is positive, the current signal is applied to the first switch and when the clock signal is zero, the current signal is applied to the second switch. The first switch will output the current signal during the first half of the clock cycle to a first output or a second output, and the second switch will output the current signal during the second half of the clock cycle to the first output or the second output.

    摘要翻译： DAC，包括第一开关和第二开关。 第一开关接收要转换的数字信号，第二开关接收延迟时钟信号的二分之一的数字信号。 第三开关从电流源和时钟信号接收电流信号。 第三开关交替地将电流信号切换到第一和第二开关，使得当时钟信号为正时，电流信号被施加到第一开关，并且当时钟信号为零时，电流信号被施加到第二开关。 第一个开关将在时钟周期的前一半期间将当前信号输出到第一个输出或第二个输出，第二个开关将在时钟周期的后半段输出当前信号到第一个输出或第二个输出 。