公开(公告)号：EP1787136B1

公开(公告)日：2009-06-03

申请号：EP05703024.9

申请日：2005-02-22

申请人： NXP B.V.

发明人： Goel, Sandeep K.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318541

摘要： A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output cells (72), and is connected to a child TAM, CTAM [0:2]. Each wrapper input cell (75) and each wrapper output cell (72) of the child core is adapted to be connected to the parent TAM, PTAM, in addition to being connected to the child TAM, CTAM, thereby enabling the child core to be placed in the In-test and Ex-test modes at the same time, and allowing the parent and child cores to be tested in parallel.