公开(公告)号：EP3004903A1

公开(公告)日：2016-04-13

申请号：EP14733455.1

申请日：2014-05-28

申请人： Qualcomm Incorporated

发明人： SHAH, Jay Madhukar ,  SWAMYNATHAN, Chethan ,  DATTA, Animesh

IPC分类号： G01R31/3185

CPC分类号： G01R31/3177 ,  G01R31/318541

摘要： Techniques for reducing scan overhead in a scannable flop tray are described herein. In one embodiment, a scan circuit for a flop tray comprises a tri-state circuit configured to invert an input data signal and output the inverted data signal to an input of a flip-flop of the flop tray in a normal mode, and to block the data signal from the input of the flip-flop in a scan mode. The scan circuit also comprises a pass gate configured to pass a scan signal to the input of the flip-flop in the scan mode, and to block the scan signal from the input of the flip-flop in the normal mode.

摘要翻译： 本文描述了用于减少可扫描的翻转托盘中的扫描开销的技术。 在一个实施例中，用于翻转托盘的扫描电路包括三态电路，其被配置为反转输入数据信号并将反相数据信号以正常模式输出到翻转托盘的触发器的输入，并且阻塞 在扫描模式下来自触发器的输入的数据信号。 扫描电路还包括被配置为在扫描模式下将扫描信号传递到触发器的输入的通路，并且在正常模式下阻止来自触发器的输入的扫描信号。

公开(公告)号：EP2680504A1

公开(公告)日：2014-01-01

申请号：EP13000455.9

申请日：2013-01-30

申请人： Silicon Touch Technology, Inc.

发明人： Chin, Chi-Yuan ,  Chen, Kuei-Jyun

IPC分类号： H04L12/437

CPC分类号： H04L1/1809 ,  G01R31/318505 ,  G01R31/318541 ,  H04L49/109 ,  H04L49/15 ,  H04L49/25 ,  H04L49/552

摘要： A chip (110, 120, 130) applied to a serial transmission system includes an input terminal, a core circuit (114, 1 24, 1 34), an output terminal, a first transmission line, a second transmission line and a spare transmission line, where the input terminal is used to receive an input signal from a source outside the chip (110, 120, 130), the output terminal is used to output an output signal, the first transmission lines is coupled between the input terminal and the core circuit (114, 124, 134), the second transmission line is coupled between the core circuit (114, 124, 1 344) and the output terminal, and the spare transmission line is coupled between the input terminal and the output terminal. When the core circuit (114, 124, 1 34) cannot process the input terminal normally, the input signal is directly transmitted to the output terminal via the spare transmission line, and the input signal serves as the output signal to be outputted from the output terminal.

摘要翻译： 应用于串行传输系统中的芯片（110，120,130）包括：在输入端，一核心电路（114，1 24，1 34），保存到输出端，一第一传输线，第二传输线和传输 线，其中，所述输入端用于从所述芯片（110，120，130）的外部的源接收在输入信号，输出端用于输出输出信号，所述第一传输线被耦合在所述输入端子和之间 核心电路（114，124，134），第二传输线被耦合在所述核心电路（114，124，1344）和所述输出端之间，并且所述备用传输线被耦合在所述输入端子和所述输出端子之间。 当核心电路（114，124，1 34）不能处理输入端正常地，输入信号被直接反式mitted经由备用传输线的输出端，并且将输入信号作为输出信号从所述输出被输出的 终端。

公开(公告)号：EP2624000A1

公开(公告)日：2013-08-07

申请号：EP10857801.4

申请日：2010-09-27

申请人： Fujitsu Limited

发明人： ITOZAWA, Shintaro ,  NISHIO, Masahiro ,  NAKAYAMA, Hiroshi ,  ICHIMIYA, Junji ,  TAKAHASHI, Jin

IPC分类号： G01R31/28 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/318544 ,  G01R31/318541 ,  G01R31/318586

摘要： Object
An objective is to provide an integrated circuit capable of performing an operation check test for a combination circuit present in sections that are not connected by a scan chain.
Solution Means
An integrated circuit includes a first signal processing circuit in which a plurality of first combination circuits and a plurality of scan FFs (Flip Flop) are connected in an order of a scan FF, a first combination circuit, and a scan FF; a second signal processing circuit including a second combination circuit different from the first combination circuit; a first selection circuit configured to select data from a scan FF on an input side of one of the plurality of first combination circuits or data from an input terminal of the second signal processing circuit, and to output the selected data to the second combination circuit; and a second selection circuit configured to select data from another one of the plurality of first combination circuits different from the one of the plurality of first combination circuits or data from the second combination circuit, and to output the selected data to the scan FF on an output side of the another one of the plurality of first combination circuits.

摘要翻译： 目的是提供一种集成电路，其能够对未由扫描链连接的部分中存在的组合电路进行操作检查测试。 解决方案装置集成电路包括第一信号处理电路，其中多个第一组合电路和多个扫描FF（触发器）以扫描FF，第一组合电路和扫描FF的顺序连接; 第二信号处理电路，包括与第一组合电路不同的第二组合电路; 第一选择电路，被配置为从所述多个第一组合电路之一的输入侧的扫描FF或来自所述第二信号处理电路的输入端的数据中选择数据，并将所选择的数据输出到所述第二组合电路; 以及第二选择电路，被配置为从与所述多个第一组合电路不同的所述多个第一组合电路中的另一个组合电路或来自所述第二组合电路的数据中选择数据，并且将所选择的数据输出到所述扫描FF， 多个第一组合电路中的另一个的输出侧。

公开(公告)号：EP2619765A1

公开(公告)日：2013-07-31

申请号：EP11771296.8

申请日：2011-09-21

申请人： Qualcomm Incorporated

发明人： RAO, Hari M. ,  YOON, Sei Seung ,  CHEN, Nan

IPC分类号： G11C29/32 ,  G01R31/3185

CPC分类号： G01R31/318541 ,  G11C11/417 ,  G11C29/32

摘要： A scan test of a first latch and a second latch couples a given scan value to the input of the first latch, to switch the first latch to a state corresponding to the scan value, uncouples the scan value from the first latch to latch the first latch at that state, couples the output of the first latch while latched at that state to the input of the second latch to switch the second latch to that state, and uncoupling the output of the first latch from the input of the second latch to latch the second latch at that state.

公开(公告)号：EP1851560B1

公开(公告)日：2010-04-14

申请号：EP06710860.5

申请日：2006-02-09

申请人： NXP B.V.

发明人： WAAYERS, Thomas F., c/o Philips I.P. & Standards ,  MORREN, Richard, c/o Philips I.P. & Standards

IPC分类号： G01R31/3185

CPC分类号： G01R31/318541 ,  G01R31/318594

公开(公告)号：EP1257837B1

公开(公告)日：2008-07-09

申请号：EP00978829.0

申请日：2000-11-16

申请人： Mentor Graphics Corporation

发明人： RAJSKI, Janusz ,  TYSZER, Jerzy ,  TAMARAPALLI, Nagesh

IPC分类号： G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters - circuits (FIG. 10) used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

公开(公告)号：EP1865601A1

公开(公告)日：2007-12-12

申请号：EP06011821.3

申请日：2006-06-08

申请人： STMicroelectronics S.r.l.

发明人： Casarsa, Marco

IPC分类号： H03K3/037 ,  H03K19/173 ,  G01R31/3185

CPC分类号： H03K19/1737 ,  G01R31/318541 ,  H03K3/037

摘要： The present invention relates to an asynchronous set-reset circuit device (20) for improving the quality requirement and reducing the patterns generation time in the testing activity normally performed by using an Automatic Test Patterns Generation (ATPG) tool, said circuit device including a core portion (17) comprising a couple of logic gates (22, 23) with at least two inputs each. The set-reset circuit (20) of the invention further includes:
- a logic gate structure (8) provided upstream with respect to the core portion (17) for driving one respective input of the couple of logic gates;
- feedback connections (18, 19) between the outputs of the logic gates (22, 23) and respective inputs of the logic gate structure (8);
- further inputs of the logic gate structure (8) receiving a couple of test command signals (TR, TS).

摘要翻译： 本发明涉及一种异步设置复位电路装置（20），用于在通常使用自动测试模式生成（ATPG）工具执行的测试活动中改善质量要求并减少模式生成时间，所述电路装置包括核心 部分（17）包括具有至少两个输入的逻辑门（22,23）。 本发明的设置复位电路（20）还包括： - 逻辑门结构（8），其相对于所述核心部分（17）设置在上游，用于驱动所述逻辑门对中的一个相应输入; - 逻辑门（22,23）的输出与逻辑门结构（8）的相应输入之间的反馈连接（18,19）。 - 接收一对测试命令信号（TR，TS）的逻辑门结构（8）的另外的输入。

公开(公告)号：EP1864379A1

公开(公告)日：2007-12-12

申请号：EP05718255.2

申请日：2005-03-23

申请人： Freescale Semiconductor Inc.

发明人： PRIEL, Michael ,  KUZMIN, Dan ,  ROZEN, Anton

IPC分类号： H03K3/3562 ,  G01R31/3185

CPC分类号： G01R31/318541 ,  G01R31/318536 ,  H03K3/0375

摘要： A method (400) for race prevention and a device (100) that has race prevention capabilities. The method (400) includes: selectively providing (410) data or scan data to a input latching logic, activating (420) the input latching logic for a first scan mode activation period, introducing (430) a substantial time shift between the first scan mode activation period and a second scan mode activation period, and activating (440) a output latching logic, connected to the input latching logic for a second scan mode activation period. The device (100) includes: an interface logic (110), a input latching logic (120), a output latching logic (130) and a control logic (150). The interface logic (110) is adapted to selectively provide data or scan data to the input latching logic (120). The control logic (150) is adapted to introduce a substantial time difference between an end point of a first scan mode activation period of the input latching logic (120) and between a start point of a second scan mode activation period of the output latching logic (130).

公开(公告)号：EP1787136A1

公开(公告)日：2007-05-23

申请号：EP05703024.9

申请日：2005-02-22

申请人： Koninklijke Philips Electronics N.V.

发明人： Goel, Sandeep K.

IPC分类号： G01R31/3185

CPC分类号： G01R31/318536 ,  G01R31/318541

摘要： A wrapper architecture has a parent core A and a child core B. The parent core A comprises scan chains (70), wrapper input cells (71), wrapper output cells (74) and a parent TAM, PTAM [0:2]. Likewise, the child core comprises scan chains (76), wrapper input cells (75) and wrapper output cells (72), and is connected to a child TAM, CTAM [0:2]. Each wrapper input cell (75) and each wrapper output cell (72) of the child core is adapted to be connected to the parent TAM, PTAM, in addition to being connected to the child TAM, CTAM, thereby enabling the child core to be placed in the In-test and Ex-test modes at the same time, and allowing the parent and child cores to be tested in parallel.

公开(公告)号：EP1085896B1

公开(公告)日：2007-05-16

申请号：EP99957020.3

申请日：1999-06-15

申请人： DeveloGen Israel Ltd.

发明人： HORNIK, Vered ,  AFARGAN, Michel, M. ,  GELLERMAN, Gary

IPC分类号： A61K38/04 ,  A61K38/12 ,  C07K7/64 ,  C07K14/655

CPC分类号： C07K14/6555 ,  A61K38/00 ,  G01R31/31816 ,  G01R31/318541

摘要： Novel peptides which are conformationally constrained backbone cyclized somatostatin analogs, having somatostatin receptor sub-type selectivity are disclosed. These patterns of receptor subtype selectivity provide compounds having improved therapeutic utility. Methods for synthesizing the somatostatin analogs and for screening of the somatostatin analogs are also disclosed. Furthermore, pharmaceutical compositions comprising somatostatin analogs, and methods of using such compositions are disclosed.