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    DATENTRÄGER
    1.
    发明授权
    DATENTRÄGER 有权

    公开(公告)号：EP1046125B1

    公开(公告)日：2008-12-24

    申请号：EP99950639.7

    申请日：1999-09-28

    申请人： NXP B.V.

    发明人： TIMM, Volker ,  MALZAHN, Ralf ,  EBER, Wolfgang ,  BERGER, Dominik ,  KESSELS, Jozef, L., W. ,  KRAMER, Torsten

    IPC分类号： G06K7/00 ,  G06K19/07

    CPC分类号： G06K19/07769 ,  G06K19/07 ,  G06K19/0701 ,  G06K19/073

    摘要： The invention relates to a data carrier, especially a chip card. Said chip card comprises a data processing unit and at least one contact-less interface. The data processing unit by means of which said interface can be connected to a read/write device for exchanging data signals and for taking up electrical power for operating the data processing unit. Said data processing unit at least mainly consists of logic modules which are operated at least in a substantially asynchronous mode ('asynchronous logic'). The inventive data carrier is characterized in that it optimally utilizes the power supplied to it while the signal processing steps performed in it are protected from being cracked.

    摘要翻译： 数据载体，特别是芯片卡。 所述芯片卡包括数据处理单元和至少一个非接触式接口。 数据处理单元借助于所述数据处理单元，所述接口可以连接到用于交换数据信号和用于操作数据处理单元的电力的读/写设备。 所述数据处理单元至少主要由至少以基本异步模式（“异步逻辑”）操作的逻辑模块组成。 本发明的数据载体的特征在于，在其中执行的信号处理步骤被防止破裂的同时，它最佳地利用提供给它的功率。

    DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY
    2.
    发明授权
    DATA PROCESSING CIRCUIT WITH MULTIPLEXED MEMORY 有权
    带记忆复用数据处理电路

    公开(公告)号：EP1639478B1

    公开(公告)日：2007-08-29

    申请号：EP04736433.6

    申请日：2004-06-09

    申请人： NXP B.V.

    发明人： KESSELS, Jozef, L., W. ,  ANDREJIC, Ivan

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1642 ,  G06F13/1673 ,  Y02D10/14

    摘要： A data processing apparatus contains several processing circuits each operating under control of its own periodic clock signal, so that the clock signals may have different frequencies and/or can be autonomous. The several processing circuits each have an output for outputting memory access requests, which remain at the output for a validity duration interval defined by the clock signal of the particular processor. A multiplexing circuit multiplexes the access requests to a memory. The memory needs a minimum memory repetition period before it can accept an access request following acceptance of a preceding access request. The clock periods of the processing circuits are longer than the minimum memory repetition period. A timing circuit selects acceptance time points at which each particular access request from a first data processing circuit is accepted. The time point at which the particular request is accepted is always within the validity duration interval in which the particular access request is made. The timing circuit varies the position of the acceptance time points within the validity duration intervals, so that the position is delayed to make room for previously accepting an access request from another processor. The position is subsequently moved back toward a start of the validity duration interval in successive steps during application of successive access requests from the first data processing circuit.