公开(公告)号：EP1611498B1

公开(公告)日：2010-03-10

申请号：EP04722371.4

申请日：2004-03-22

申请人： NXP B.V.

发明人： PESSOLANO, Francesco

IPC分类号： G06F1/32

CPC分类号： G06F9/3842 ,  G06F1/3203 ,  G06F9/3806

摘要： During execution of a program of computer instructions, the execution of branch instructions is detected, and in response, the activity of processing circuitry during execution of instructions following a branch instruction is measured. Respective information about the measured activity is recorded for each of a plurality of branch instructions. The measured activity is later used to adapt the power consumption mode of the processing circuitry after encountering the respective branch instructions.

公开(公告)号：EP1620829B1

公开(公告)日：2009-08-26

申请号：EP04728617.4

申请日：2004-04-21

申请人： NXP B.V.

发明人： PESSOLANO, Francesco

IPC分类号： G06K19/073 ,  G07F7/10 ,  H04L9/06

CPC分类号： G06K19/073 ,  G06K19/07363 ,  H04L9/003 ,  H04L2209/125

摘要： The electronic circuit executes operations dependent on secret information. Power supply current dependency on the secret information is cloaked by drawing additional power supply current. A plurality of processing circuits (102, 106) executes respective parts of the operations dependent on the secret information. An activity monitor circuit (12a, b, 14), coupled to receive pairs of processing signals coming into and out of respective ones of the processing circuits, derive activity information from each pair of processing signals. The activity monitoring circuit (12a, b, 14) generates a combined activity signal indicative of a sum of power supply currents that will be consumed by the processing circuits (102, 106) dependent on the processing signals. A current drawing circuit connected to the power supply connections is controlled by the activity monitor circuit (12a, b, 14) to draw a cloaking current controlled by the combined activity signal, so that power supply current variations dependent on the secret information are cloaked in a sum of the cloaking current and current drawn by the processing circuits (102, 106).

公开(公告)号：EP1646941B1

公开(公告)日：2010-12-15

申请号：EP04744489.8

申请日：2004-07-05

申请人： NXP B.V.

发明人： PESSOLANO, Francesco

IPC分类号： G06F9/38

CPC分类号： G06F9/3848

摘要： A system and method for predicting the outcome of a conditional branch within a computer system, the method comprising the steps of identifying (105) the occurrence of a conditional branch, obtaining (106) data relating to system activity since a previous branch, comparing (110) said data with data relating to previous system activity, and predicting (108) the branch outcome based on such comparison. An activity monitor (Figure 3 - 20) may be used to provide the data relating to system activity.

公开(公告)号：EP1540828B1

公开(公告)日：2009-02-25

申请号：EP03795107.6

申请日：2003-08-06

申请人： NXP B.V.

发明人： PESSOLANO, Francesco ,  VAN DIJK, Victor, E., S.

IPC分类号： H03M5/02

CPC分类号： H04L25/0266 ,  G01R31/318538 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates to a method for coding information in an electronic circuit and an electronic circuit for coding information, said circuit comprising at least two electrically coupled signal paths (X0, X1). The invention is based on the idea that cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first path (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0), an output signal (X) having a second logic value is produced.

公开(公告)号：EP1839104A2

公开(公告)日：2007-10-03

申请号：EP06710653.4

申请日：2006-01-10

申请人： NXP B.V.

发明人： PESSOLANO, Francesco ,  MEIJER, Rinze, I., M., P. ,  PINEDA DE GYVEZ, Jose, D., J. ,  HEIJLIGERS, Marcus, J., M.

IPC分类号： G06F1/32

CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A digital system 1 comprises receiving means (5) for receiving one or more performance indicators or parameters from software (6) controlling the execution of an application (3). Based on the performance indicators received by the receiving means (5), a tuning circuit (7) is provided for tuning the frequency (f), supply voltage (Vdd) and/or the transistor threshold voltage (Vb) of the digital system (1). In addition, pipeline configuration means (8) are provided for configuring the pipeline of the digital system (1) based on a pipeline depth determined by selecting means (10). The selecting means (10) is configured to select the pipeline depth (Pd) based on the frequency (f), supply voltage (Vdd), transistor threshold voltage (Vb), and according to whether the application requires maximum throughput or minimum latency.