公开(公告)号：EP2122956A1

公开(公告)日：2009-11-25

申请号：EP08702591.2

申请日：2008-02-07

申请人： NXP B.V.

发明人： FILIPPI, Alessio ,  SERBETLI, Semih ,  WANG, Ying

IPC分类号： H04L27/26

CPC分类号： H04L27/2675 ,  H04L5/0007 ,  H04L5/0048 ,  H04L27/2665 ,  H04L27/2695

摘要： A method of synchronizing multi-carrier systems is provided, wherein the method comprises inserting a predefined frequency domain signal into a signal on a transmitter side of a multi- carrier system and multi-carrier modulating the signal. Furthermore, the method comprises transmitting the multi-carrier modulated signal via a carrier channel to a receiving side of the multi-carrier system, and synchronizing the multi-carrier modulated signal by using the predefined frequency domain signal portion of the multi-carrier modulated signal.

公开(公告)号：EP3442146A1

公开(公告)日：2019-02-13

申请号：EP17186056.2

申请日：2017-08-11

申请人： NXP B.V.

发明人： SERBETLI, Semih ,  VAN HOUTUM, Wim ,  GULTEKIN, Yunus Can ,  WILLEMS, Frans M.J.

IPC分类号： H04L1/00 ,  H04L27/34 ,  H03M13/25

摘要： An input selector for selecting an input of a convolution encoder of a transmitter is disclosed. The input selector comprises a shaper block and an input-select block. The shaper block is configured to receive an input comprising a first number of input bits, the shaper block configured to generate a shaped bit stream corresponding to the first number of input bits. The input-select block is configured to generate an encoder input bit stream for the encoder based on the shaped bit stream, wherein the input-select block generates the encoder input bit stream such that, when input into the encoder, a first bit of the encoder input bit stream sets a state of the encoder in order that a subsequent second bit of the encoder input bit stream causes the encoder to generate a bit of the shaped bit stream at a pre-determined position in an encoder output bit stream.

公开(公告)号：EP2409450A1

公开(公告)日：2012-01-25

申请号：EP10712560.1

申请日：2010-03-19

申请人： NXP B.V.

发明人： SERBETLI, Semih ,  HEKSTRA, Andries, Pieter

IPC分类号： H04L5/00

CPC分类号： H04L5/0044 ,  H04L5/0023 ,  H04L25/0204 ,  H04L27/265

摘要： A processor (110) is disclosed for processing a plurality of Fourier-transformed instances of a symbol, each instance being comprised in one of a plurality of frequency-divided multiplexed subcarriers, said processor being arranged to estimate, for each instance, the channel gain and the inter-carrier interference contribution to said symbol from neighboring subcarriers due to a time-varying channel response of the received signal,; and combine the instances into a single representation of said symbol based on the estimated channel gain and the inter-carrier interference contributions. A receiver comprising such a processor and a method for processing such signals are also disclosed.

摘要翻译： 公开了一种处理器（110），用于处理符号的多个傅里叶变换实例，每个实例被包括在多个分频多路复用子载波中的一个中，所述处理器被安排为针对每个实例来估计信道增益 以及由于接收信号的时变信道响应对来自相邻子载波的所述符号的载波间干扰贡献; 并且基于估计的信道增益和载波间干扰贡献，将实例组合成所述符号的单个表示。 还公开了一种包括这种处理器的接收机和用于处理这种信号的方法。

公开(公告)号：EP3605851A1

公开(公告)日：2020-02-05

申请号：EP19186950.2

申请日：2019-07-18

申请人： NXP B.V.

发明人： SERBETLI, Semih ,  ENGIN, Nur

IPC分类号： H03M13/37 ,  H03M13/29 ,  H03M13/45

摘要： Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded (110) to produce a first decoded output, which is subsequently encoded (120), and error characteristics of the encoded first decoded output are assessed (130). The input signal is again decoded (140) (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.