公开(公告)号：EP2297859A1

公开(公告)日：2011-03-23

申请号：EP09762139.5

申请日：2009-06-09

申请人： NXP B.V.

发明人： DILONARDO, Angelo Raffaele ,  ENGIN, Nur

IPC分类号： H03M13/27 ,  H03M13/29

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2764 ,  H03M13/2957 ,  H03M13/6519 ,  H03M13/6525 ,  H03M13/6544

摘要： A data processing system, a turbo decoding system, an address generator and a method of reconfiguring a turbo decoding method is provided. The data processing system (101) comprises the turbo decoding system (100). The turbo decoding system (100) comprises electronic circuits. The electronic circuits comprises: a memory (108), the address generator (102), and a Soft Input Soft Output decoder (106). The address generator (102) is operative to produce a sequence of addresses according to an interleaving scheme. The address generator can support multiple interleaving schemes. The address generator (102) is operative to receive reconfiguration information. The address generator (102) is operative to reconfigure during operational use the interleaving scheme in dependency on the reconfiguration information.

公开(公告)号：EP3128426B1

公开(公告)日：2019-05-01

申请号：EP16180731.8

申请日：2016-07-22

申请人： NXP B.V.

发明人： ENGIN, Nur ,  KAPOOR, Ajay

IPC分类号： G06F11/10

公开(公告)号：EP2418779A2

公开(公告)日：2012-02-15

申请号：EP11175619.3

申请日：2011-07-27

申请人： NXP B.V.

发明人： TANG, Weihua ,  ENGIN, Nur ,  STEENHOF, Frits Anthonie ,  KLAASSEN, Marc ,  HEKSTRA, Andries Pieter ,  SAWITZKI, Sergei Valerjewisch

IPC分类号： H03M13/41

CPC分类号： H03M13/4176 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.

摘要翻译： 各种实施例涉及多标准维特比解码器。 基于约束长度，生成多项式和码率的可编程值，多标准维特比解码器可以遵循特定的卷积码标准。 在给定的时间，多标准维特比解码器可以通过信道接收各种卷积码，并且可以使用各种形式的追溯方法处理它们。 各种实施例包括分支度量单位和路径度量单位，其包括基于可编程值的值可以或可以不是活动的各种子单元。 各种实施例还使得多标准维特比解码器能够处理不同形式的卷积码，例如尾巴码。 在一些实施例中，多标准维特比解码器也可以同时处理至少两个卷积码。

公开(公告)号：EP3605851A1

公开(公告)日：2020-02-05

申请号：EP19186950.2

申请日：2019-07-18

申请人： NXP B.V.

发明人： SERBETLI, Semih ,  ENGIN, Nur

IPC分类号： H03M13/37 ,  H03M13/29 ,  H03M13/45

摘要： Aspects of the present disclosure are directed to decoding signals susceptible to communication errors. As may be implemented in accordance with one or more embodiments, an input signal is decoded (110) to produce a first decoded output, which is subsequently encoded (120), and error characteristics of the encoded first decoded output are assessed (130). The input signal is again decoded (140) (e.g., with a delay), using the encoded first decoded output and the assessed error characteristics thereof to assess a reliability characteristic of bits in the input signal. A second decoded output is then provided with errors corrected therein based on the assessed reliability characteristic.

公开(公告)号：EP3128426A3

公开(公告)日：2017-04-12

申请号：EP16180731.8

申请日：2016-07-22

申请人： NXP B.V.

发明人： ENGIN, Nur ,  KAPOOR, Ajay

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

摘要： An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

摘要翻译： 公开了包括耦合到封装逻辑的SRAM模块的集成电路（IC）器件。 封装器逻辑包括被配置为根据ECC编码方案对输入数据进行编码并且将编码的输入数据输出到SRAM模块的纠错码（ECC）编码器，被配置为对从SRAM模块接收到的输出数据进行解码的ECC解码器，输出 经解码的输出数据以及将解码信息写回到SRAM模块;耦合到ECC解码器的错误控制器，其被配置为根据ECC编码方案来控制ECC解码器;以及中央控制器，其耦合到封装器的组件 逻辑和SRAM模块，以控制封装逻辑和SRAM模块的组件之间的操作。

公开(公告)号：EP3128427A1

公开(公告)日：2017-02-08

申请号：EP16180733.4

申请日：2016-07-22

申请人： NXP B.V.

发明人： KAPOOR, Ajay ,  ENGIN, Nur ,  THOEN, Steven Mark ,  PINEDA DE GYVEZ, Jose de Jesus

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C29/52 ,  H03M13/353

摘要： In accordance with an embodiment of the invention, an integrated circuit (IC) device is disclosed. In the embodiment, the IC device includes an SRAM module, wrapper logic coupled to the SRAM module, a context source, and an ECC profile controller coupled to the context source and to the wrapper logic, the ECC profile controller configured to select an ECC profile in response to context information received from the context source for use by the wrapper logic.

摘要翻译： 在与本发明的实施例中，集成电路雅舞蹈（IC）装置游离缺失盘。 在实施例中，IC器件包括在SRAM模块，包装器逻辑，其耦合到SRAM模块，上下文源，并且在耦合到所述上下文源和包装器逻辑ECC简档控制器，所述ECC简档控制器配置成选择一个ECC轮廓 响应于上下文信息从上下文源接收到用于由包装器逻辑使用。

公开(公告)号：EP3128426A2

公开(公告)日：2017-02-08

申请号：EP16180731.8

申请日：2016-07-22

申请人： NXP B.V.

发明人： ENGIN, Nur ,  KAPOOR, Ajay

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

摘要： An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

公开(公告)号：EP2418779A3

公开(公告)日：2012-07-04

申请号：EP11175619.3

申请日：2011-07-27

申请人： NXP B.V.

发明人： TANG, Weihua ,  ENGIN, Nur ,  STEENHOF, Frits Anthonie ,  KLAASSEN, Marc ,  HEKSTRA, Andries Pieter ,  SAWITZKI, Sergei Valerjewisch

IPC分类号： H03M13/41

CPC分类号： H03M13/4176 ,  H03M13/4107 ,  H03M13/4169 ,  H03M13/6519

摘要： Various embodiments relate to a multi-standard Viterbi decoder. Based on programmable values for constraint length, generator polynomials, and code rate, the multi-standard Viterbi decoder may adhere to a specific convolutional code standard. At a given time, the multi-standard Viterbi decoder may receive a variety of convolutional codes through a channel and may process them using various forms of the trace back method. Various embodiments include a branch metric unit and path metric unit that include a variety of sub-units that may or may not be active based on the value of the programmable value. Various embodiments also enable the multi-standard Viterbi decoder to handle different forms of convolutional codes, such as tail-biting codes. In some embodiments, the multi-standard Viterbi decoder may also process at least two convolutional codes concurrently.