LOW SPURIOUS SYNTHESIZER CIRCUIT AND METHOD
    2.
    发明公开
    LOW SPURIOUS SYNTHESIZER CIRCUIT AND METHOD 审中-公开
    具有低的果酱和程序合成电路

    公开(公告)号:EP2926456A1

    公开(公告)日:2015-10-07

    申请号:EP12889269.2

    申请日:2012-11-29

    IPC分类号: H03L7/099 H03L7/085 H03L7/18

    摘要: An offset phase locked loop synthesizer comprising: an input; an output; a voltage controlled oscillator (VCO), the VCO output coupled to the synthesizer output; a phase frequency detector having a reference input, a feed- back input, and an output; a mixer having a first mixer input coupled to the synthesizer input and a second mixer input coupled to the VCO output; a first divider for frequency dividing a signal by a first value and having an input coupled to the mixer output and an output coupled to the second input of the phase frequency detector; a second divider for frequency dividing a signal by a second value and having an input coupled to the synthesizer input and an output coupled to the reference input of the phase frequency detector; and a low pass filter coupled between the output of the phase frequency detector and the VCO input.

    FREQUENCY DETERMINATION CIRCUIT AND METHOD
    3.
    发明公开
    FREQUENCY DETERMINATION CIRCUIT AND METHOD 审中-公开
    FREQUENZBESTIMMUNGSSCHALTKREIS UND VERFAHRENDAFÜR

    公开(公告)号:EP2872904A1

    公开(公告)日:2015-05-20

    申请号:EP13819817.1

    申请日:2013-07-08

    IPC分类号: G01R23/12

    CPC分类号: G01R23/02 H03L7/095 H03L7/183

    摘要: Circuits and methods for identifying or verifying frequencies are disclosed herein. A frequency verification circuit comprises: an input port for receiving an input signal; a phase frequency difference detector for determining a difference in phase and frequency between the input signal and a feedback signal and for providing a control signal based on the detected difference; a voltage controlled crystal oscillator for producing an output signal based on the control signal; and a feedback loop including a feedback divider for frequency dividing the output signal by a factor R to produce the feedback signal, the feedback divider being programmable to a plurality of values of the factor R to correspond to a plurality of different test frequencies.

    摘要翻译: 本文公开了用于识别或验证频率的电路和方法。 频率验证电路包括:用于接收输入信号的输入端口; 相位差检测器,用于确定输入信号和反馈信号之间的相位和频率差,并且用于基于检测到的差异提供控制信号; 用于产生基于所述控制信号的输出信号的压控晶体振荡器; 以及包括反馈分配器的反馈回路,所述反馈分配器用于将所述输出信号分频为因子R以产生所述反馈信号,所述反馈分配器可编程为所述因子R的多个值,以对应于多个不同的测试频率。

    ULTRA LOW PHASE NOISE SIGNAL SOURCE

    公开(公告)号:EP2873152B1

    公开(公告)日:2018-12-12

    申请号:EP13820321.1

    申请日:2013-07-08

    IPC分类号: H03B5/00 H03L7/185

    摘要: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.

    DIGITALLY COMPENSATED PHASE LOCKED OSCILLATOR
    5.
    发明公开
    DIGITALLY COMPENSATED PHASE LOCKED OSCILLATOR 审中-公开
    数字补偿相律OSC

    公开(公告)号:EP3072240A1

    公开(公告)日:2016-09-28

    申请号:EP13897882.0

    申请日:2013-11-25

    IPC分类号: H03L7/08 H03L1/02 H03L7/085

    CPC分类号: H03L7/0991 H03L1/026 H03L7/16

    摘要: A digitally compensated phase locked oscillator (DCPLO) is disclosed herein. The DCPLO comprises: a DCPLO input for receiving a reference signal at a known frequency; a DCPLO output for outputting a signal at a desired frequency; a phased locked loop (PLL), the phased locked loop comprising: a phase frequency detector, an oscillator, and a PLL output coupled to the output; a first direct digital synthesizer (DDS), the first DDS having an output coupled to the PLL to supply a DDS signal to the PLL for adjusting the frequency within the PLL so as to maintain phase lock over the operating temperature; a temperature sensor; and a processor coupled to the first DDS, the phase frequency detector, and the temperature sensor, the processor configured to set the frequency of the first DDS according to a temperature sensed by the temperature sensor.

    ULTRA LOW PHASE NOISE SIGNAL SOURCE
    7.
    发明公开
    ULTRA LOW PHASE NOISE SIGNAL SOURCE 审中-公开
    具有非常低相位噪声源

    公开(公告)号:EP2873152A1

    公开(公告)日:2015-05-20

    申请号:EP13820321.1

    申请日:2013-07-08

    IPC分类号: H03B5/00 H03L7/24

    摘要: An apparatus and method for providing an output signal. The apparatus comprises an input for receiving a reference signal, an oscillator for providing an output signal, and an offset signal generator for frequency multiplying the reference signal to generate an offset signal that has a plurality of frequency products in a plurality of frequency bands. The apparatus further includes a mixer for mixing the offset signal with the output signal to produce a combined signal, an offset frequency selector for controllably selecting a frequency band of the offset signal, and a difference detector for detecting a difference between the reference signal and the combined signal and for providing a control signal to the oscillator based on the detected difference.