公开(公告)号：EP2454735B1

公开(公告)日：2020-12-09

申请号：EP10730021.2

申请日：2010-07-01

Applicant: Netlist, Inc.

Inventor： LEE , Hyun ,  BHAKTA, Jayesh, R.

IPC: G11C5/02 ,  G11C5/06

公开(公告)号：EP2454735A1

公开(公告)日：2012-05-23

申请号：EP10730021.2

申请日：2010-07-01

Applicant: Netlist, Inc.

Inventor： LEE , Hyun ,  BHAKTA, Jayesh, R.

IPC: G11C5/02 ,  G11C5/06

CPC classification number: G06F12/00 ,  G11C5/025 ,  G11C5/04 ,  G11C5/066 ,  G11C8/12

Abstract: A memory system and method utilizing one or more memory modules is provided. The memory module includes a plurality of memory devices and a controller configured to receive control information from a system memory controller and to produce module control signals. The memory module further includes a plurality of circuits, for example byte-wise buffers, which are configured to selectively isolate the plurality of memory devices from the system memory controller. The circuits are operable, in response to the module control signals, to drive write data from the system memory controller to the plurality of memory devices and to merge read data from the plurality of memory devices to the system memory controller. The circuits are distributed at corresponding positions separate from one another.