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    DIGITAL TRANSMISSION SYSTEM AND DIGITAL TRANSMISSION METHOD
    1.
    发明公开
    DIGITAL TRANSMISSION SYSTEM AND DIGITAL TRANSMISSION METHOD 审中-公开

    公开(公告)号：EP3493433A1

    公开(公告)日：2019-06-05

    申请号：EP18215726.3

    申请日：2008-01-16

    申请人： Nippon Telegraph and Telephone Corporation ,  NTT Electronics Corporation

    发明人： KISAKA, Yoshiaki ,  OHARA, Takuya ,  AISAWA, Shigeki ,  MIYAMOTO, Yutaka ,  TAKEI, Kazuhito ,  ENDOH, Yasuyuki ,  MIURA, Katsuyoshi ,  NIKAIDO, Tadanobu ,  TOMIZAWA, Masahito

    IPC分类号： H04J3/00 ,  H04L1/00 ,  H04L29/08

    摘要： A digital transmission system (1403-1409) includes a rate adjusting means (1403, 1404) for adjusting the bit rate of a plurality of types of client signals to a bit rate range that can be accommodated in a digital frame transparently by inserting a dummy pattern, comprising a frame synchronization pattern, using a specific fixed frame, into the fixed frame for client signals other than the client signal having the highest bit rate among the plurality of types of client signals to increase the bit rate of the client signals. The number of bits of the dummy pattern and the number of bits of the client signal before the rate adjustment results in a rate M:N (where M and N are natural numbers) to construct the specific fixed frame, and the values N and M are set so that (Bc ±Ac) x (M + N)/N results in a bit rate range that can be accommodated in the digital frame, where the bit rate and the frequency accuracy of the client signal are Bc and ±Ac, respectively, wherein the dummy pattern of M bits is inserted to every N bits of the client signals.
    The digital transmission system (1403-1409) further comprises rate restoring means (1408, 1409) for restoring the rate to an original bit rate of a client signal by discriminating the dummy pattern area using the frame synchronization pattern and deleting the dummy pattern on a receiver side.

    CLOCK REPRODUCTION SIGNAL GENERATION METHOD AND CLOCK REPRODUCTION CIRCUIT
    4.
    发明公开
    CLOCK REPRODUCTION SIGNAL GENERATION METHOD AND CLOCK REPRODUCTION CIRCUIT 审中-公开
    TAKTWIEDERGABE-SIGNALERZEUGUNGSVERFAHREN UND TAKTWIEDERGABESCHALTUNG

    公开(公告)号：EP2290856A1

    公开(公告)日：2011-03-02

    申请号：EP09754529.7

    申请日：2009-04-22

    申请人： NTT Electronics Corporation

    发明人： ENDOH, Yasuyuki ,  TAKEI, Kazuhito ,  MIURA, Katuyoshi ,  NIKAIDO, Tadanobu ,  KISAKA, Yoshiaki

    IPC分类号： H04J3/07 ,  H04L7/033

    CPC分类号： H04J3/0691 ,  H03L7/00 ,  H04J3/07

    摘要： The present invention is directed for reducing jitters occurring in a recovered clock signal CK since even when multiple items of specific data are inserted in one cycle of generation period for an enable period, a deviation of an output cycle of the enable period can be eliminated.
    According to the present invention, as shown in FIG. 5(a) , when a signal for clock recovery ED is generated, which is formed by alternately generating enable periods EN having a ratio (N/M) of N clocks' client data to M clocks' line data and disable periods D1 to D4, a phase of the disable period D2 is advanced by a phase corresponding to the disable period (such as one clock period) during the enable period with reference to phase information added to the signal for clock recovery ED as shown in FIG. 5(c) when a stuff pulse in the line data is detected as indicated by the symbol m0 in FIG. 5(b) , thereby generating the signal for clock recovery ED.

    摘要翻译： 本发明旨在减少在恢复的时钟信号CK中发生的抖动，因为即使当多个特定数据项在生成周期的一个周期内被插入使能周期时，可以消除使能周期的输出周期的偏差。 根据本发明，如图1所示， 如图5（a）所示，当产生用于时钟恢复ED的信号时，通过交替地产生具有N个时钟的客户端数据与M个时钟线数据的比率（N / M）的使能周期EN和禁用周期D1至D4 参考图5所示的时钟恢复ED信号的相位信息，禁用期间D2的相位在使能期间内与禁止期间（例如一个时钟周期）相对应的相位前进。 如图5（c）所示，当检测到行数据中的填充脉冲时，如图5中的符号m0所示。 如图5（b）所示，从而产生用于时钟恢复ED的信号。