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公开(公告)号：EP4209909A1
公开(公告)日：2023-07-12
申请号：EP22214031.1
申请日：2022-12-16
IPC分类号： G06F9/50 , G06F9/54 , H04L41/0803 , H04L41/0895
摘要： To dynamically allow chaining of logical processing units comprising endpoints, at least a type of an endpoint, and address information whereto connect the endpoint is configured, wherein the type of the endpoint is either a host port type or a logical processing unit type. During offloading from a central processing unit one or more functions to be performed by at least one further processing unit, the central processing unit is interacting with the one or more logical processing units via endpoints of the host port type and logical processing units are interacting via endpoints of the logical processing unit port type, the interaction using the address information.
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公开(公告)号：EP4086910A1
公开(公告)日：2022-11-09
申请号：EP21172198.0
申请日：2021-05-05
发明人： JIANG, Zhewei , CHOW, Hungkei
IPC分类号： G11C11/54 , G11C7/10 , G11C7/16 , G11C27/02 , G06N3/063 , G06F7/544 , G11C11/412 , G11C11/419
摘要： Multiply-accumulate (MAC) operations using In-Memory Computing are disclosed. An example apparatus includes a bitcell array to perform a MAC operation using a multibit weight and a multibit input. Each bitcell of the bitcell array includes a memory unit to store a weight bit, a multiplication unit to multiply the weight bit by an input bit, and an output capacitor to store the result. Sample-and-hold circuits coupled to each column of output capacitors are used to store a charge to a holding capacitor representing a partial MAC result for the column. Input bits are sent to the bitcell array to be multiplied by the multibit weights in a series of input cycles to generate the MAC result. Input bit significance is represented by reducing the charge stored to the holding capacitors by half at each input cycle, and weight bit significance is represented by the position of the holding capacitor.
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