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    CIRCUITS FOR CONVERTING SFQ-BASED RZ AND NRZ SIGNALING TO BILEVEL VOLTAGE NRZ SIGNALING
    6.
    发明公开
    CIRCUITS FOR CONVERTING SFQ-BASED RZ AND NRZ SIGNALING TO BILEVEL VOLTAGE NRZ SIGNALING 审中-公开

    公开(公告)号：EP4135197A1

    公开(公告)日：2023-02-15

    申请号：EP22179480.3

    申请日：2022-06-16

    申请人： Northrop Grumman Systems Corporation

    发明人： KNEE, Derek L. ,  KETCHEN, Mark B. ,  BURNETT, Randall M.

    IPC分类号： H03K19/195

    摘要： Edge-sensitive, state-based single flux quantum (SFQ) based circuitry and related methods convert return-to-zero (RZ) or non-return-to-zero (NRZ) encoded SFQ-pulse-based signals to bilevel NRZ phase signals that can subsequently be converted to bilevel voltage signals by an output amplifier (OA). The SFQ-based circuitry can be integrated with a current amplification stage of a driver that can be coupled to a stage of the OA. The SFQ-based circuitry can be made to be compatible with RQL-encoded input signals that can be either RZ or NRZ The SFQ-based circuitry can thus be compatible with both wave-pipelined (WPL) and phasemode (PML) RQL circuitry. Because the SFQ-based circuitry and related methods are edge-sensitive and state-based, they can function at system clock rates in excess of 1 GHz with reduced glitches and improved bit error rates as compared to other superconducting RZ-NRZ conversion circuitry and methods.

    SUPERCONDUCTING GATE MEMORY CIRCUIT
    10.
    发明公开
    SUPERCONDUCTING GATE MEMORY CIRCUIT 审中-公开

    公开(公告)号：EP3507907A2

    公开(公告)日：2019-07-10

    申请号：EP17762256.0

    申请日：2017-08-15

    申请人： Northrop Grumman Systems Corporation

    发明人： BURNETT, Randall M. ,  HERR, Quentin P.

    IPC分类号： H03K3/38 ,  G11C11/44 ,  H03K19/195

    摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.