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1.发明公开VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS WITH ASYMMETRIC MULTI-THREADING 审中-公开矢量处理器配置为使用不对称多线程的可变长度向量运行
公开(公告)号：EP3254195A1
公开(公告)日：2017-12-13
申请号：EP16747020.2
申请日：2016-01-28
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , HURTLEY, Paul , SENTHILVELAN, Murugappan , BALZOLA, Pablo , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F9/50
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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2.发明公开VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING IMPLICITLY TYPED INSTRUCTIONS 审中-公开矢量处理器配置为使用隐式类型的指令在可变长度向量上运行
公开(公告)号：EP3254204A1
公开(公告)日：2017-12-13
申请号：EP16746995.6
申请日：2016-01-27
发明人： MOUDGILL, Mayan , GLOSSNER, C. John , HOANE, Arthur Joseph , HURTLEY, Paul , KALASHNIKOV, Vitaly
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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公开(公告)号：EP3103015A1
公开(公告)日：2016-12-14
申请号：EP15746333.2
申请日：2015-02-03
发明人： GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Muragappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3885 , G06F9/46
摘要： A processing device identifies a set of software threads having instructions waiting to issue. For each software thread in the set of the software threads, the processing device binds the software thread to an available hardware context in a set of hardware contexts and stores an identifier of the available hardware context bound to the software thread to a next available entry in an ordered list. The processing device reads an identifier stored in an entry of the ordered list. Responsive to an instruction associated with the identifier having no dependencies with any other instructions among the instructions waiting to issue, the processing device issues the instruction waiting to issue to the hardware context associated with the identifier.
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公开(公告)号：EP3103302B1
公开(公告)日：2019-08-07
申请号：EP15746535.2
申请日：2015-02-02
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5.发明公开VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING DIGITAL SIGNAL PROCESSING INSTRUCTIONS 审中-公开配置为使用数字信号处理指令以可变长度向量操作的矢量处理器
公开(公告)号：EP3254207A1
公开(公告)日：2017-12-13
申请号：EP16747024.4
申请日：2016-01-28
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , HURTLEY, Paul , SENTHILVELAN, Murugappan , BALZOLA, Pablo , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F15/76
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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6.发明公开VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS USING GRAPHICS PROCESSING INSTRUCTIONS 审中-公开矢量处理器配置为使用图形处理指令在可变长度向量上运行
公开(公告)号：EP3254187A1
公开(公告)日：2017-12-13
申请号：EP16747031.9
申请日：2016-01-29
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur, Joseph , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F9/30
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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7.发明公开MONOLITHIC VECTOR PROCESSOR CONFIGURED TO OPERATE ON VARIABLE LENGTH VECTORS 审中-公开配置为可变长度向量运行的单片矢量处理器
公开(公告)号：EP3254186A1
公开(公告)日：2017-12-13
申请号：EP16746998.0
申请日：2016-01-27
发明人： MOUDGILL, Mayan , NACER, Gary, J. , GLOSSNER, C., John , HOANE, Arthur Joseph , HURTLEY, Paul , SENTHILVELAN, Murugappan , BALZOLA, Pablo , KALASHNIKOV, Vitaly , AGRAWAL, Sitij
IPC分类号： G06F9/30
CPC分类号： G06F15/8053 , G06F9/3001 , G06F9/30021 , G06F9/30036 , G06F9/30101 , G06F9/30109 , G06F9/30112 , G06F9/30141 , G06F9/3836 , G06F9/3855 , G06F15/7828 , G06F15/7839 , G06F15/8076 , G06F17/142
摘要： A computer processor is disclosed. The computer processor may comprise a vector unit comprising a vector register file comprising one or more registers to hold a varying number of elements. The computer processor may further comprise processing logic configured to implicitly type each of the varying number of elements in the vector register file. The computer processor may be implemented as a monolithic integrated circuit.
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8.发明公开METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS 有权方法和设备，处理器流水线产生控制信号
公开(公告)号：EP3103302A1
公开(公告)日：2016-12-14
申请号：EP15746535.2
申请日：2015-02-02
发明人： GLOSSNER, C., John , NACER, Gary, J. , SENTHILVELAN, Murugappan , KALASHNIKOV, Vitaly , HOANE, Arthur, J. , D'ARCY, Paul , IANCU, Sabin, D. , WANG, Shenghong
IPC分类号： H04W72/12
CPC分类号： G06F9/3822 , G06F9/3836 , G06F9/3853
摘要： A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.
摘要翻译： 计算机处理器的链接位解码器接收对指令流。 的链接位解码器选择一组从指令流的指令。 的链接位译码器提取从指令流的各指令一指定的比特，以产生链接的位序列。 的链接位解码器解码链的位的序列。 的链接位解码器标识的在视图链接的比特的解码序列的指令所选择的组中的零间或多个指令流的依赖关系。 的链接位解码器输出控制信号，以使得所述处理器的一个或多个管线级鉴于指令组序列中所识别的零个或多个指令流的依赖性以执行所选择的组的指令。
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