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    PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT
    2.
    发明公开
    PROCESSOR WITH ADVANCED OPERATING SYSTEM SUPPORT 审中-公开
    具有先进操作系统支持的处理器

    公开(公告)号：EP3308270A1

    公开(公告)日：2018-04-18

    申请号：EP16808001.8

    申请日：2016-05-17

    申请人： Optimum Semiconductor Technologies, Inc.

    发明人： MOUDGILL, Mayan ,  NACER, Gary ,  GLOSSNER, C., John ,  HOANE, Arthur, Joseph ,  HURTLEY, Paul ,  SENTHILVELAN, Murugappan

    IPC分类号： G06F9/46

    CPC分类号： G06F9/30189 ,  G06F9/3005 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/462

    摘要： A computer processor may include a plurality of hardware threads. The computer processor may further include state processor logic for a state of a hardware thread. The state processor logic may include per thread logic that contains state that is replicated in each hardware thread of the plurality of hardware threads and common logic that is independent of each hardware thread of the plurality of hardware threads. The computer processor may further include single threaded mode logic to execute instructions in a single threaded mode from only one hardware thread of the plurality of hardware threads. The computer processor may further include second mode logic to execute instructions in a second mode from more than one hardware thread of the plurality of hardware threads simultaneously. The computer processor may further include witching mode logic to switch between the first mode and the second mode.

    METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS
    7.
    发明公开
    METHOD AND APPARATUS FOR ENABLING A PROCESSOR TO GENERATE PIPELINE CONTROL SIGNALS 有权
    方法和设备，处理器流水线产生控制信号

    公开(公告)号：EP3103302A1

    公开(公告)日：2016-12-14

    申请号：EP15746535.2

    申请日：2015-02-02

    申请人： Optimum Semiconductor Technologies, Inc.

    发明人： GLOSSNER, C., John ,  NACER, Gary, J. ,  SENTHILVELAN, Murugappan ,  KALASHNIKOV, Vitaly ,  HOANE, Arthur, J. ,  D'ARCY, Paul ,  IANCU, Sabin, D. ,  WANG, Shenghong

    IPC分类号： H04W72/12

    CPC分类号： G06F9/3822 ,  G06F9/3836 ,  G06F9/3853

    摘要： A chaining bit decoder of a computer processor receives an instruction stream. The chaining bit decoder selects a group of instructions from the instruction stream. The chaining bit decoder extracts a designated bit from each instruction of the instruction stream to produce a sequence of chaining bits. The chaining bit decoder decodes the sequence of chaining bits. The chaining bit decoder identifies zero or more instruction stream dependencies among the selected group of instructions in view of the decoded sequence of chaining bits. The chaining bit decoder outputs control signals to cause one or more pipelines stages of the processor to execute the selected group of instructions in view of the identified zero or more instruction stream dependencies among the group sequence of instructions.

    摘要翻译： 计算机处理器的链接位解码器接收对指令流。 的链接位解码器选择一组从指令流的指令。 的链接位译码器提取从指令流的各指令一指定的比特，以产生链接的位序列。 的链接位解码器解码链的位的序列。 的链接位解码器标识的在视图链接的比特的解码序列的指令所选择的组中的零间或多个指令流的依赖关系。 的链接位解码器输出控制信号，以使得所述处理器的一个或多个管线级鉴于指令组序列中所识别的零个或多个指令流的依赖性以执行所选择的组的指令。

    OPPORTUNITY MULTITHREADING IN A MULTITHREADED PROCESSOR WITH INSTRUCTION CHAINING CAPABILITY
    8.
    发明公开
    OPPORTUNITY MULTITHREADING IN A MULTITHREADED PROCESSOR WITH INSTRUCTION CHAINING CAPABILITY 审中-公开
    多样性 - 多元化北美多种多样的食品添加剂麻省理工学院ANWEISUNGSVERKETTUNGSKAPAZITÄT

    公开(公告)号：EP3103011A1

    公开(公告)日：2016-12-14

    申请号：EP15746129.4

    申请日：2015-02-03

    申请人： Optimum Semiconductor Technologies, Inc.

    发明人： WANG, Shenghong ,  GLOSSNER, C., John ,  NACER, Gary, J.

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3826 ,  G06F9/3818 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/46

    摘要： A computing device determines that a current software thread of a plurality of software threads having an issuing sequence does not have a first instruction waiting to be issued to a hardware thread during a clock cycle. The computing device identifies one or more alternative software threads in the issuing sequence having instructions waiting to be issued. The computing device selects, during the clock cycle by the computing device, a second instruction from a second software thread among the one or more alternative software threads in view of determining that the second instruction has no dependencies with any other instructions among the instructions waiting to be issued. Dependencies are identified by the computing device in view of the values of a chaining bit extracted from each of the instructions waiting to be issued. The computing device issues the second instruction to the hardware thread.

    摘要翻译： 计算设备确定具有发布序列的多个软件线程的当前软件线程在时钟周期期间不具有等待发送到硬件线程的第一指令。 计算设备识别发布序列中的一个或多个备选软件线程，其中有等待发出的指令。 考虑到在等待等待的指令中确定第二指令与任何其他指令没有任何依赖关系，计算设备在计算设备的时钟周期期间选择来自一个或多个替代软件线程中的第二软件线程的第二指令 被发行。 考虑到从每个等待发出的指令提取的链接位的值，计算设备识别依赖关系。 计算设备向硬件线程发出第二条指令。