IMPLEMENTATION FOR A HIGH PERFORMANCE BCD DIVIDER
    1.
    发明公开
    IMPLEMENTATION FOR A HIGH PERFORMANCE BCD DIVIDER 审中-公开
    高性能BCD分割器的实现

    公开(公告)号:EP3161615A1

    公开(公告)日:2017-05-03

    申请号:EP15739111.1

    申请日:2015-06-27

    IPC分类号: G06F7/491 G06F7/535

    摘要: Embodiments of an apparatus are disclosed for performing arithmetic operations on provided operands. The apparatus may include a fetch unit, and an arithmetic logic unit (ALU). The fetch unit may be configured to retrieve two operands responsive to receiving an instruction, wherein the operands include binary-coded decimal values. The ALU may be configured to scale a value of each of the operands, and then compress the scaled values of the operands. The compressed values of the operands may include fewer data bits than the corresponding scaled values. The ALU may be further configured to estimate a portion of a result of the operation dependent upon the compressed values of the operands.

    摘要翻译: 公开了用于对所提供的操作数执行算术运算的装置的实施例。 该装置可以包括提取单元和算术逻辑单元(ALU)。 提取单元可以被配置为响应于接收指令来检索两个操作数,其中操作数包括二进制编码的十进制值。 ALU可以被配置为缩放每个操作数的值,然后压缩操作数的缩放值。 操作数的压缩值可以包括比对应的缩放值更少的数据位。 ALU可以进一步被配置为根据操作数的压缩值来估计操作结果的一部分。