公开(公告)号：EP2278824A4

公开(公告)日：2012-03-14

申请号：EP10766837

申请日：2010-04-20

申请人： PANASONIC CORP

发明人： TAKATORI MASAHIRO ,  SUZUKI SATOSHI ,  KASE DAISUKE ,  GOTANDA CHIKARA

IPC分类号： H04N13/04 ,  G09G5/00 ,  G09G5/36 ,  G09G5/377 ,  H04N5/445 ,  H04N7/173

CPC分类号： H04N13/007 ,  H04N5/44504 ,  H04N5/44508 ,  H04N13/0011 ,  H04N21/4882 ,  H04N21/4886 ,  H04N21/814

摘要： An image processor includes a 3D image output section for outputting a 3D image; an average parallax calculator for calculating a parallax level of each target pixel based on a lefty-eye image and a right-eye image, and calculating an average screen parallax level based on the parallax level; a data acquisition section for detecting the type of 3D image or a characteristic of synthesized image; a correcting and synthesizing section for correcting the average screen parallax level depending on the type of 3D image or the characteristic of synthesized image, setting a corrected average parallax level as parallax to be added to the caption or OSD, adding the parallax to the caption or OSD, and synthesizing a caption or OSD with parallax; and an image synthesizer for superimposing the caption or OSD synthesized image with parallax on the 3D image.

公开(公告)号：EP1635558A4

公开(公告)日：2009-03-18

申请号：EP04735126

申请日：2004-05-27

申请人： PANASONIC CORP

发明人： GOTANDA CHIKARA ,  NIO YUTAKA ,  NAGATA KOUICHIRO

IPC分类号： G02B17/00 ,  G02B17/06 ,  G02B17/08 ,  G02B27/14 ,  G02B27/22 ,  H04N5/08 ,  H04N5/44 ,  H04N5/46 ,  H04N5/63 ,  H04N7/52

CPC分类号： H04N7/52 ,  H04N5/08 ,  H04N5/4401 ,  H04N5/46 ,  H04N5/63 ,  H04N21/43632 ,  H04N21/4436

摘要： A power-down determining circuit uses a clock signal applied from a multiplying circuit and horizontal and vertical sync signals applied from a TMDS decoder circuit to calculate horizontal and vertical frequencies, then compares the calculated horizontal and vertical frequencies with those stored in advance to determine whether an input digital signal has a decodable video format, and then outputs a power-down control signal indicative of a determination result. In this way, when an input digital signal has no decodable format, the power-down control signal causes a video/audio processing circuit to enter a power-down mode.