摘要:
A power-down determining circuit uses a clock signal applied from a multiplying circuit and horizontal and vertical sync signals applied from a TMDS decoder circuit to calculate horizontal and vertical frequencies, then compares the calculated horizontal and vertical frequencies with those stored in advance to determine whether an input digital signal has a decodable video format, and then outputs a power-down control signal indicative of a determination result. In this way, when an input digital signal has no decodable format, the power-down control signal causes a video/audio processing circuit to enter a power-down mode.
摘要:
A method for determining the aspect ratio of an image signal and an image apparatus using the same is provided. The image apparatus includes a sync signal separation unit (130) which separates a sync signal from an image signal, an aspect ratio determination unit (140) which determines an aspect ratio of the image signal using a voltage level of the separated sync signal, and a signal processing unit (530) which processes the image signal according to the aspect ratio.
摘要:
An image decoder comprises first clock regeneration means (20) for deriving a first clock signal (21) from a time stamp signal (19) extracted from a digital transmission stream (5); decoder means (8) for decoding a digital video stream (7) to provide a first digital video signal (9) at a first frame frequency, the first digital video signal being synchronized with the first clock signal (21); graphic generator means (10); superposition means (12) for superposing the first digital video signal (9) and a graphic signal (11) on each other to provide a first synthesized digital video signal (15) synchronized with the first clock signal (21); and D/A converter means (16) for converting the first synthesized digital video signal (15) to an analog signal (17), wherein there are no missing frames or distortion occurring in the displayed image even though the digital video and graphic signals are superposed.
摘要:
A display synchronization signal generator capable of displaying a stable image regardless of changes in a transmission speed of a received digital broadcast signal in a digital broadcast receiver. The display synchronization signal generator includes a speed difference detector, a vertical period change amount detector, a vertical synchronization signal generator, a pixel clock signal generator, and a horizontal synchronization signal generator. The vertical period change amount detector detects a change amount in a vertical period of an image to be displayed, based on a detected speed difference. The vertical synchronization signal generation unit generates a vertical synchronization signal with a period that is changed based on the change amount detected by the vertical period change amount detector. The pixel clock signal generator generates a pixel clock signal based on a basic clock signal. The horizontal synchronization signal generator generates a horizontal synchronization signal in response to the pixel clock signal.
摘要:
In a synchronous processing circuit in the figure, an LPF (1) separates a vertical synchronizing separation signal (6) from a composite signal (5) from the outside, a 1/2 frequency division circuit (4) outputs a vertical phase detection signal (9) obtained by dividing the vertical synchronizing separation signal (6) into 1/2, a phase delay unit (2) to which the composite signal (5) is input outputs a plurality of different phase-delayed horizontal synchronizing signals (19 to 24), and a vertical synchronizing signal reproducing circuit (3) uses the vertical synchronizing separation signal (6) and the plurality of phase-delayed horizontal synchronizing signals (19 to 24) to output a vertical synchronizing signal (8) for which a phase relation with a horizontal synchronizing signal is determined.
摘要:
A television monitor display with video signal processing comprises a source (SM) of a video display signal (Y) including a sync component (S). A video processor (U1) is coupled to process the video display signal (Y). A sync separator (SS) is coupled to generate separated synchronizing signals (Sy) from the sync component (S) of the video display signal (Y). A video amplifier (100) is coupled to the sync separator (SS) and the video processor (U1) and generates an output video signal (Ys+) wherein a sync component (S+) of the output video signal is increased in amplitude in accordance with the separate synchronizing signals (Sy) coupled to the video amplifier (100).