公开(公告)号：EP1557857A4

公开(公告)日：2009-06-10

申请号：EP04733130

申请日：2004-05-14

Applicant: PANASONIC CORP

Inventor： HASEGAWA KAZUYUKI ,  OE YOSHINAO ,  MIZOKAMI KANAME ,  NAKAUE HIROKAZU ,  KADO HIROYUKI

IPC: C23C14/24 ,  H01J9/02 ,  H01J11/12 ,  H01J11/22 ,  H01J11/24 ,  H01J11/26 ,  H01J11/34 ,  H01J11/40 ,  H01J11/02

CPC classification number: H01J11/12 ,  H01J9/02 ,  H01J11/40

Abstract: A plasma display panel comprising a dielectric layer (9) which is so formed as to cover a scan electrode (5) and a sustain electrode (6) formed on a front substrate (4) and a protective layer (10) formed on the dielectric layer (9) is disclosed wherein the protective layer (10) contains silicon and nitrogen. The protective layer (10) is composed of magnesium oxide containing silicon at a concentration from 5 × 1018 atoms/cm3 to 2 × 1021 atoms/cm3 and nitrogen at a concentration from 1 × 1018 atoms/cm3 to 8 × 1021 atoms/cm3. With this constitution, the plasma display panel has a short discharge delay and excellent discharge generation response to voltage application, and enables to suppress change of discharge delay to temperature change.