公开(公告)号：EP0733285A1

公开(公告)日：1996-09-25

申请号：EP95927941.0

申请日：1995-08-30

申请人： PHILIPS ELECTRONICS N.V.

发明人： CLINE, Ronald, Lee

IPC分类号： H03K19

CPC分类号： H03K19/17708

摘要： A PLD comprises a programmable first AND array whose inputs are selectively connectable to input lines and whose outputs are selectively connectable to a programmable second OR array. The PLD further comprises a programmable third AND array whose inputs are selectively connectable to the input lines, and whose outputs are fixedly connected to inputs of a fixed fourth OR array. The outputs from the second OR array are also connected in a fixed manner to the fourth OR array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.

公开(公告)号：EP0733285B1

公开(公告)日：1999-11-10

申请号：EP95927941.5

申请日：1995-08-30

申请人： Koninklijke Philips Electronics N.V.

发明人： CLINE, Ronald, Lee

IPC分类号： H03K19/177

CPC分类号： H03K19/17708

摘要： A PLD comprises a programmable first AND array whose inputs are selectively connectable to input lines and whose outputs are selectively connectable to a programmable second OR array. The PLD further comprises a programmable third AND array whose inputs are selectively connectable to the input lines, and whose outputs are fixedly connected to inputs of a fixed fourth OR array. The outputs from the second OR array are also connected in a fixed manner to the fourth OR array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.