公开(公告)号：EP3326061A1

公开(公告)日：2018-05-30

申请号：EP16742134.6

申请日：2016-07-11

Applicant: Qualcomm Incorporated

Inventor： MAHURIN, Eric ,  GOLAB, Jakub Pawel

IPC: G06F9/30

CPC classification number: G06F9/3887 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30134 ,  G06F15/82

Abstract: A first register has a lane storing first input data and a second register has a lane storing second input data elements. A width of the lane of the second register is equal to a width of the lane of the first register. A single-instruction-multiple-data (SIMD) lane has a lane width equal to the width of the lane of the first register. The SIMD lane is configured to perform a sliding window operation on the first input data elements in the lane of the first register and the second input data elements in the lane of the second register. Performing the sliding window operation includes determining a result based on a first input data element stored in a first position of the first register and a second input data element stored in a second position of the second register. The second position is different from the first position.

公开(公告)号：EP3311294A1

公开(公告)日：2018-04-25

申请号：EP16731280.0

申请日：2016-06-16

Applicant: Nordic Semiconductor ASA

Inventor： RUSTEN, Joar Olai

IPC: G06F13/40

CPC classification number: G06F13/4282 ,  G06F9/30134 ,  G06F9/544 ,  G06F13/1673 ,  G06F13/4059

Abstract: An electronic data processing device comprises: a processor (1); a serial interface comprising a connection for incoming data (16) and a connection for outgoing data (18); a hardware serial-interface controller (6) for controlling the serial interface; and a reception buffer (22) for receiving incoming data. The processor is arranged automatically to read data written to the reception buffer. The device is arranged so that the processor can indicate to the serial interface controller that it is unable to accept data. The controller is arranged to respond to incoming data by sending a rejection message from the outgoing serial connection and to prevent incoming data from being placed in the reception buffer.

公开(公告)号：EP3218799A1

公开(公告)日：2017-09-20

申请号：EP15859621.3

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： EVANS, Arnold, Kerry ,  OULD-AHMED-VALL, Elmoustapha

IPC: G06F9/30 ,  G06F9/06

CPC classification number: G06F9/30145 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30134 ,  G06F9/3802

Abstract: In one embodiment, a processor includes 32-bit and 64-bit machine level instructions to compute a 4D Z-curve Index. A processor decode unit is configured to decode a z-curve ordering instruction having three source operands, each operand associated with one of a first, second, or third coordinate and a processor execution unit is configured to execute the decoded instruction before outputting the 4D Z-curve index to a location specified by a destination operand.

Abstract translation: 在一个实施例中，处理器包括用于计算4D Z-曲线索引的32位和64位机器级指令。 处理器解码单元被配置为解码具有三个源操作数的z曲线排序指令，每个操作数与第一，第二或第三坐标中的一个相关联，并且处理器执行单元被配置为在输出4D Z之前执行解码的指令 - 曲线索引到由目标操作数指定的位置。

公开(公告)号：EP1548576A3

公开(公告)日：2017-04-19

申请号：EP05002557.6

申请日：1996-12-17

Applicant: Intel Corporation

Inventor： Mennemeier, Larry M. ,  Vakkalagadda, Ramamohan R. ,  Mittal, Millind ,  Lin, Derrick ,  Eitan, Benny ,  Peleg, Alex ,  Bistry, David ,  Kowashi, Eiichi ,  Glew, Andrew ,  Dulong, Carole

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to operands used by the first set of instructions to the physical register file in a stock referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

Abstract translation: 一种用于执行浮点和紧缩数据说明，用一个单一的物理寄存器文件的方法和装置也被混叠。 。根据本发明的一个方面，提供了一种处理器做包括一解码单元，映射单元，以及存储单元。 解码单元被配置为指令和其操作数从至少一个指令集包括至少一个第一和第二组指令进行解码。 所述存储单元包括一个物理寄存器文件。 所述映射单元被配置为在一个股票引用方式使用由第一组的说明将物理寄存器文件的操作数。 另外，映射单元被配置成映射在一个非堆叠参考方式使用由所述第二组指令到相同的物理寄存器堆的操作数。

公开(公告)号：EP3118738A1

公开(公告)日：2017-01-18

申请号：EP16177445.0

申请日：2016-07-01

Applicant: NXP B.V.

Inventor： GUNTUR, Surendra ,  FABRIE, Sebastien Antonius Josephus ,  PINDEA DE GYVEZ, Jose

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3005 ,  G06F9/30098 ,  G06F9/30123 ,  G06F9/30134 ,  G06F9/30181 ,  G06F9/327 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3867 ,  G06F9/3885

Abstract: In an embodiment, a method for processing instructions in a microcontroller is disclosed. In the embodiment, the method involves, upon receipt of an interrupt while an instruction is being executed, completing execution of the instruction by a shadow functional unit and, upon servicing the interrupt, terminating re-execution of the instruction and updating a main register file with the result of the execution of the instruction by the shadow functional unit.

Abstract translation: 在一个实施例中，公开了一种用于处理微控制器中的指令的方法。 在本实施例中，该方法涉及在执行指令时接收到中断，完成阴影功能单元完成指令的执行，并且在服务中断时终止重新执行指令并更新主寄存器文件 由阴影功能单元执行指令的结果。

公开(公告)号：EP2771885A4

公开(公告)日：2017-01-18

申请号：EP11874746

申请日：2011-10-27

Applicant: HEWLETT PACKARD ENTPR DEV LP

Inventor： GOLAB WOJCIECH ,  PICKETT MATTHEW D ,  KARP ALAN H

IPC: G11C19/00 ,  G06F9/30 ,  G06F12/00 ,  G06F15/78

CPC classification number: G11C7/1036 ,  G06F5/00 ,  G06F9/30032 ,  G06F9/30134 ,  G06F9/544 ,  G06F15/7821 ,  G06F2209/521 ,  G11C19/188 ,  G11C19/287

公开(公告)号：EP1543418B1

公开(公告)日：2016-03-16

申请号：EP03783831.5

申请日：2003-08-06

Applicant: MMagix Technology Limited

Inventor： O'SULLIVAN, Daniel, Shane

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/00

CPC classification number: G06F9/3867 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3879 ,  G06F9/3885 ,  G06F9/526 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus, method, and system for synchronicity independent, resource delegating, power and instruction optimizing processor is provided where instructions are delegated between various processing resources of the processor. An Integer Processing Unit (IPU) of the processor delegates complicated mathematical instructions to a Mathematical Processing Unit (MPU) of the processor. Furthermore, the processor puts underutilized processing resources to sleep thereby increasing power usage efficiency. A cache of the processor is also capable of accepting delegated operations from the IPU. As such, the cache performs various logical operations on delegated requests allowing it to lock and share memory without requiring extra processing cycles by the entire processor. With the processor, execution instructions are optimized reducing the complexity of the processor, throughput is increased as delegation to multiple processing resources is scalable, and power usage efficacy is increased as underutilized and/or waiting processing resources may sleep when not active.

公开(公告)号：EP2523101B1

公开(公告)日：2014-06-04

申请号：EP12174228.2

申请日：2007-11-14

Applicant: Soft Machines, Inc.

Inventor： Abdallah, Mohammed

IPC: G06F9/38

CPC classification number: G06F9/30123 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/342 ,  G06F9/3808 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/4843

Abstract: The present invention relates to a system comprising: a cache adapted to store a temporary prefetched value that has a one-to-one mapping with a consuming instruction, wherein the temporary prefeteched value has a corresponding name and wherein the consuming instruction explicitly references the corresponding name; an execution unit to execute the consuming instruction in conjunction with the temporary prefetched value; and a scheduling unit to release the location of the temporary prefeteched value in the cache after the execution unit executes the consuming instruction.

公开(公告)号：EP2101267B1

公开(公告)日：2013-10-09

申请号：EP09159693.2

申请日：2004-08-05

Applicant: IP-First LLC

Inventor： Hooker, Rodney E

IPC: G06F12/08

CPC classification number: G06F9/30134 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/383 ,  G06F9/3842 ,  G06F12/0875 ,  G06F12/1045

公开(公告)号：EP2603852A1

公开(公告)日：2013-06-19

申请号：EP11733692.5

申请日：2011-06-13

Applicant: ARM Limited

Inventor： GRISENTHWAITE, Richard, Roy

IPC: G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/30134 ,  G06F9/3824

Abstract: A data processing system 2 includes a stack pointer register 26, 28, 30, 32 storing a stack pointer value for use in stack access operations to a stack data store 44, 46, 48, 50. Stack alignment checking circuitry 36 which is selectively disabled may be provided to check memory address alignment of the stack pointer value associated with a stack memory access. The action of the stack alignment checking circuitry 36 is independent of any further other alignment checking performed in respect of all memory accesses. Thus, general alignment checking circuitry 38 may be provided and independently selectively disabled in respect of any memory access.