公开(公告)号：EP0642095B1

公开(公告)日：2002-05-22

申请号：EP94306540.9

申请日：1994-09-06

申请人： PHILIPS ELECTRONICS UK LIMITED ,  Koninklijke Philips Electronics N.V.

发明人： Hughes, John Barry, c/o Philips Res.Lab. ,  Moulding, Kenneth William, c/o Philips Res.Lab.

IPC分类号： G06G7/186 ,  G06G7/184

CPC分类号： G06G7/1865

公开(公告)号：EP0642095A3

公开(公告)日：1996-07-31

申请号：EP94306540.9

申请日：1994-09-06

申请人： PHILIPS ELECTRONICS UK LIMITED ,  PHILIPS ELECTRONICS N.V.

发明人： Hughes, John Barry, c/o Philips Res.Lab. ,  Moulding, Kenneth William, c/o Philips Res.Lab.

IPC分类号： G06G7/186

CPC分类号： G06G7/1865

摘要： A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which during a first phase of a clock cycle an input current is fed to the inputs of the current memory cells and during a second phase of a clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2) . A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell (N2) and an inverted, scaled version of the current stored in the first memoy cell (M1).

公开(公告)号：EP0642095A2

公开(公告)日：1995-03-08

申请号：EP94306540.9

申请日：1994-09-06

申请人： PHILIPS ELECTRONICS UK LIMITED ,  PHILIPS ELECTRONICS N.V.

发明人： Hughes, John Barry, c/o Philips Res.Lab. ,  Moulding, Kenneth William, c/o Philips Res.Lab.

IPC分类号： G06G7/186

CPC分类号： G06G7/1865

摘要： A switched current bilinear integrator comprising interconnected current memory cells (M1, M2) in which during a first phase of a clock cycle an input current is fed to the inputs of the current memory cells and during a second phase of a clock cycle an inverted version (A1) of the input current is fed to the inputs of the current memory cells. The output of the integrator is obtained by combining the output (optionally scaled) of the first current memory cell (M1) with an inverted (A2) version of the output (optionally scaled) of the second memory cell (M2) .
A lossy integrator may be formed by feeding back to the input a scaled version of the current stored in the second current memory cell (N2) and an inverted, scaled version of the current stored in the first memoy cell (M1).

摘要翻译： 一种开关电流双线性积分器，包括互连的当前存储单元（M1，M2），其中在时钟周期的第一阶段期间，将输入电流馈送到当前存储器单元的输入端，并且在时钟周期的第二阶段期间， （A1）输入到当前存储单元的输入端。 通过将第一当前存储器单元（M1）的输出（可选地缩放）与第二存储器单元（M2）的输出（可选地缩放）的反相（A2）版本组合来获得积分器的输出。 可以通过将存储在第二当前存储器单元（N2）中的电流的缩放版本和存储在第一备忘单元（M1）中的电流的反转的缩放版本反馈给输入来形成有损积分器。