专利检索 ap:("PLESSEY OVERSEAS LIMITED") AND inv:"Knight, William Lawrence" 第 1 页

1.

发明授权
Circuit arrangement for use in an integrated circuit having built in self-test design 失效
标题翻译：在自检中设计的集成电路中使用的电路布置

公开(公告)号：EP0190494B1

公开(公告)日：1990-09-19

申请号：EP85308853.2

申请日：1985-12-05

申请人： PLESSEY OVERSEAS LIMITED

发明人： Burrows, David Frank , Paraskeva, Mark , Knight, William Lawrence

IPC分类号： G01R31/318 , G06F11/26

CPC分类号： G01R31/318547 , G01R31/318541 , G01R31/318572

2.

发明公开
Circuit arrangement for use in an integrated circuit having built in self-test design 失效
标题翻译：用于集成电路的电路具有内置自测试的配置。

公开(公告)号：EP0190494A1

公开(公告)日：1986-08-13

申请号：EP85308853.2

申请日：1985-12-05

申请人： PLESSEY OVERSEAS LIMITED

发明人： Burrows, David Frank , Paraskeva, Mark , Knight, William Lawrence

IPC分类号： G01R31/318 , G06F11/26

CPC分类号： G01R31/318547 , G01R31/318541 , G01R31/318572

摘要： A circuit arrangement for use in an integrated circuit having a built-in self test design, the circuit arrangement comprising first and second gates (8, 3) coupled to a flip-flop (2) via a third gate (4). The present invention provides a multiplexer (M) coupled to one input of the first gate (8), the multiplexer (M) being controllable by a control signal to feed either input data or output data of the circuit arrangement to said one input of the first gate (8) and a fourth gate (13) coupled to an input of the second gate (3), the fourth gate (13) having an input connected to receive a signal dependent on the control signal to the data selector means (M).