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    INTEGRATED CIRCUIT MARGIN MEASUREMENT AND FAILURE PREDICTION DEVICE
    5.
    发明公开
    INTEGRATED CIRCUIT MARGIN MEASUREMENT AND FAILURE PREDICTION DEVICE 审中-公开

    公开(公告)号：EP4328596A2

    公开(公告)日：2024-02-28

    申请号：EP23220748.0

    申请日：2018-11-15

    申请人： Proteantecs Ltd.

    发明人： LANDMAN, Evelyn ,  COHEN, Shai ,  DAVID, Yahel ,  FAYNEH, Eyal ,  WEINTROB, Inbar

    IPC分类号： G01R31/28

    摘要： A semiconductor integrated circuit (IC) comprising a signal path combiner, comprising a plurality of input paths and an output path. The IC comprises a delay circuit having an input electrically connected to the output path, the delay circuit delaying an input signal by a variable delay time to output a delayed signal path. The IC may comprise a first storage circuit electrically connected to the output path and a second storage circuit electrically connected to the delayed signal path. The IC comprises a comparison circuit that compares outputs of the signal path combiner and the delayed signal, wherein the comparison circuit comprises a comparison output provided in a comparison data signal to at least one mitigation circuit.