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1.发明公开Method of, and arrangement for, generating a clock signal from a biphase modulated digital signal 失效方法和装置，用于从一个双相位调制数字信号的时钟脉冲信号。
公开(公告)号：EP0497391A1
公开(公告)日：1992-08-05
申请号：EP92200023.7
申请日：1992-01-07
发明人： Rhebergen, Gertjan
CPC分类号： H04L7/0334 , H04L25/4904
摘要： A clock signal is generated, from a biphase modulated, digital signal, by means of two samples (TF, TB) per symbol interval, T. This pair of samples are spaced at about T / 4.
The clock is generated by, firstly, shifting the pair of samples (TF, TB) until one of them (TF) is very close to the zero - crossing point of the biphase signal. The other sample (TB) will then be located at a maximum or minimum. During this procedure, the separation of the two samples remains fixed at T / 4. The separation is then made variable. In this way, TF can track the zero crossing point while TB remains at the maximum or minimum, despite jitter in the incoming signal.摘要翻译： 时钟信号产生，从调制数字信号双相，由每符号间隔的两个样品（TF，TB）的手段，T.这对样本在约T / 4，通过，产生的时钟首先间隔开， 移位对样本（TF，TB），直到它们（TF）中的一个非常接近零 - 双相位信号的交叉点。 另一样品（TB）然后将位于最大值或最小值。 在此过程中，两种样品的分离保持固定在T / 4的分离然后可变。 以这种方式，而TB保持在最大或最小，尽管在输入信号中的抖动TF可以跟踪过零点。
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2.发明授权Method of, and arrangement for, generating a clock signal from a biphase modulated digital signal 失效用于产生从一个两相的时钟脉冲信号的方法和装置调制的数字信号
公开(公告)号：EP0497391B1
公开(公告)日：1996-05-29
申请号：EP92200023.7
申请日：1992-01-07
发明人： Rhebergen, Gertjan
CPC分类号： H04L7/0334 , H04L25/4904
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3.发明公开Arrangement for generating pulse code modulation values in a telephone set 失效Anordnung zum Liefern von Pulskodemodulationswerten in einem Fernsprechapparat。
公开(公告)号：EP0534549A2
公开(公告)日：1993-03-31
申请号：EP92202883.2
申请日：1992-09-21
IPC分类号： H04M1/00
CPC分类号： H04M1/253
摘要： Arrangement for generating pulse code modulation values in a telephone set, comprising a microprocessor (1) which includes a working store, in which the microprocessor and the working store are connected by means of a data bus (5) and an address bus (6), further including an output circuit (3) for outputting the pulse code modulation values, an output memory connected thereto for storing the pulse code modulation values to be output, the working store and the output memory being incorporated in a single memory circuit (2). The arrangement is preferably structured in such a way that it comprises addressing means for generating, in response to the microprocessor's addressing of a random location of the output memory, an address of an output memory location to be read out.
摘要翻译： 一种用于在电话机中产生脉冲编码调制值的装置，包括一个包括工作存储器的微处理器，其中微处理器和工作存储器借助于数据总线和地址总线连接，还包括输出电路， 脉冲编码调制值，连接到其上的输出存储器，用于存储要输出的脉冲编码调制值，工作存储器和输出存储器并入单个存储器电路中。 该布置优选地以这样的方式构造，使得其包括寻址装置，用于响应于微处理器对输出存储器的随机位置的寻址，产生要读出的输出存储器位置的地址。
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4.发明公开Automatic false synchronization correction mechanism for biphase-modulated signal reception 失效自动机构用于校正误同步，用于接收双相位调制信号。
公开(公告)号：EP0625837A2
公开(公告)日：1994-11-23
申请号：EP94201405.1
申请日：1994-05-18
发明人： Rhebergen, Gertjan
CPC分类号： H04L7/0334 , H03L7/08 , H03L2207/14
摘要： The invention relates to an arrangement comprising a controllable clock signal source (1) and a decision circuit (8) for determining the polarity of a received biphase signal at two successive sampling instants in a single symbol interval. The arrangement likewise comprises a phase detector (35) with a first comparator (16) to compare the polarity samples at the two sampling instants with each other. The phase detector generates a control signal for adjusting the frequency and phase of the adjustable clock signal source (1) in response to the output signal of the first comparator. Furthermore, the arrangement comprises a second comparator (28) for comparing polarity samples at the same relative sampling instant in two successive sampling instants with each other. According to the invention the second comparator (28) will inhibit phase detector (35) in response to the output signal of this second detector. In the case of false synchronization, the output of phase detector (35) will continue to present the same signal value, so that automatically an adjustment is made of the instant of correct synchronization. This adjustment is carried out by a VCO (3) and/or phase shifter means (12).
摘要翻译： 本发明涉及在装置包括一个可控时钟信号源（1）和判定电路（8），用于确定性采矿接收双相位信号中的两个连续的采样时刻在单个符号间隔的极性。 该装置同样包括一个第一比较器（16）的极性样品在海誓山盟两个采样时刻比较的相位检测器（35）。 相位检测器基因费率用于响应于所述第一比较器的输出信号调整所述可调整时钟信号源（1）的频率和相位的控制信号。 进一步，该装置包括：用于在相同的相对采样时刻在海誓山盟两个连续的取样时刻进行比较极性的样品的第二比较器（28）。 。根据本发明的第二比较器（28）将抑制相位检测器（35）响应于该第二检测器的输出信号。 在假同步的情况下，相位检测器（35）的输出将继续提供相同的信号值，因此在调整自动确实是由正确的同步的时刻的。 这种调整是由一VCO开展（3）和/或移相器装置（12）。
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公开(公告)号：EP0392582A1
公开(公告)日：1990-10-17
申请号：EP90200734.3
申请日：1990-03-28
发明人： Rhebergen, Gertjan
IPC分类号： G01R23/15
摘要： A method of discriminating among frequencies of an a.c. voltage by means of a processor linked to the a.c. voltage, wherein, after detection of a first zero-crossing of the a.c. voltage, a looped program is initiated, the loop comprising a counter counting the number of loop cycles until a second zero-crossing is detected. Then it is determined in which preset interval the count is situated, each interval corresponding with a possibly occurring 10 frequency.
摘要翻译： 一种鉴别a.c.的频率的方法。 通过与a.c.相连的处理器来实现电压。 电压，其中，在检测到所述a.c.的第一过零点之后。 电压，启动循环程序，该循环包括计数循环次数的计数器，直到检测到第二个过零点。 然后确定计数所在的预设间隔，每个间隔对应于可能出现的10个频率。
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6.发明授权
公开(公告)号：EP0528491B1
公开(公告)日：1996-01-10
申请号：EP92202480.7
申请日：1992-08-11
发明人： Rhebergen, Gertjan
IPC分类号： H04B3/23
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公开(公告)号：EP0392582B1
公开(公告)日：1995-07-26
申请号：EP90200734.3
申请日：1990-03-28
发明人： Rhebergen, Gertjan
IPC分类号： G01R23/15
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8.发明公开
公开(公告)号：EP0534549A3
公开(公告)日：1993-07-14
申请号：EP92202883.2
申请日：1992-09-21
IPC分类号： H04M1/00
CPC分类号： H04M1/253
摘要： Arrangement for generating pulse code modulation values in a telephone set, comprising a microprocessor (1) which includes a working store, in which the microprocessor and the working store are connected by means of a data bus (5) and an address bus (6), further including an output circuit (3) for outputting the pulse code modulation values, an output memory connected thereto for storing the pulse code modulation values to be output, the working store and the output memory being incorporated in a single memory circuit (2). The arrangement is preferably structured in such a way that it comprises addressing means for generating, in response to the microprocessor's addressing of a random location of the output memory, an address of an output memory location to be read out.
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9.发明授权Arrangement for generating pulse code modulation values in a telephone set 失效安排在电话机供应Pulskodemodulationswerten
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10.发明公开Automatic false synchronization correction mechanism for biphase-modulated signal reception 失效自动机构用于校正误同步，用于接收双相位调制信号。
公开(公告)号：EP0625837A3
公开(公告)日：1995-05-24
申请号：EP94201405.1
申请日：1994-05-18
发明人： Rhebergen, Gertjan
CPC分类号： H04L7/0334 , H03L7/08 , H03L2207/14
摘要： The invention relates to an arrangement comprising a controllable clock signal source (1) and a decision circuit (8) for determining the polarity of a received biphase signal at two successive sampling instants in a single symbol interval. The arrangement likewise comprises a phase detector (35) with a first comparator (16) to compare the polarity samples at the two sampling instants with each other. The phase detector generates a control signal for adjusting the frequency and phase of the adjustable clock signal source (1) in response to the output signal of the first comparator. Furthermore, the arrangement comprises a second comparator (28) for comparing polarity samples at the same relative sampling instant in two successive sampling instants with each other. According to the invention the second comparator (28) will inhibit phase detector (35) in response to the output signal of this second detector. In the case of false synchronization, the output of phase detector (35) will continue to present the same signal value, so that automatically an adjustment is made of the instant of correct synchronization. This adjustment is carried out by a VCO (3) and/or phase shifter means (12).
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