UNIFIED FRACTIONAL SEARCH AND MOTION COMPENSATION ARCHITECTURE ACROSS MULTIPLE VIDEO STANDARDS
    2.
    发明公开
    UNIFIED FRACTIONAL SEARCH AND MOTION COMPENSATION ARCHITECTURE ACROSS MULTIPLE VIDEO STANDARDS 审中-公开
    VERGINHEITLICHTE FRAKTIONIERTE这样的展示BEGEGUNGSKOMPENSATIONSARCHITEKTUR

    公开(公告)号:EP2850834A1

    公开(公告)日:2015-03-25

    申请号:EP13727420.5

    申请日:2013-05-10

    IPC分类号: H04N7/26 H04N7/36 H04N7/46

    摘要: Methods and systems for performing at least one of video encoding and video decoding are disclosed. In one implementation, the system includes a controller configured to determine a video standard associated with a portion of the video data, each portion of the video data associated with one of a plurality of video standards. The controller is further configured to provide a set of the filter parameters which are associated with a video standard to be used for at least one of the video encoding and decoding and at least one filter configured to filter at least one reference pixel received from the reference pixel memory based, at least in part, on the provided set of filter parameters.

    摘要翻译: 公开了用于执行视频编码和视频解码中的至少一个的方法和系统。 在一个实现中,系统包括控制器,其被配置为确定与视频数据的一部分相关联的视频标准,视频数据的每个部分与多个视频标准中的一个相关联。 所述控制器还被配置为提供一组滤波器参数,所述一组滤波器参数与要用于所述视频编码和解码中的至少一个的视频标准相关联,以及至少一个滤波器,被配置为对从所述参考中接收的至少一个参考像素进行滤波 至少部分地基于所提供的一组滤波器参数。

    INTERLEAVE BLOCK PROCESSING ORDERING FOR VIDEO DATA CODING
    4.
    发明公开
    INTERLEAVE BLOCK PROCESSING ORDERING FOR VIDEO DATA CODING 审中-公开
    嵌套块处理分拣视频编码

    公开(公告)号:EP2850828A1

    公开(公告)日:2015-03-25

    申请号:EP13716699.7

    申请日:2013-04-04

    IPC分类号: H04N7/26

    摘要: Systems and methods for interleaving video sub-blocks in video coding are described herein. In one aspect, an apparatus includes a memory and a video coder. The memory stores a first video block and a second video block. The first video block and the second video block include sub-blocks. The video coder processes a first sub-block of the first video block according to a first process and a second process, and processes a second sub-block of the first video block according to the first process and the second process after processing the first sub-block of the first video block according to the first process and the second process. Further, the video coder processes a first sub-block of the second video block according to the first process before processing the second sub-block of the first video block according to the first process.