摘要:
A Viterbi decoder (20) for recovering the original bit data stream that was convolutionally encoded as a code symbol stream in a Code Division Multiple Access (CDMA) mobile communication system (22). The decoder (20) simultaneously decodes at the several data rates associated with certain multirate vocoders. The decoder (20) can decode at an unknown data rate in either continuous or framed packed modes. It accomplishes this by simultaneously decoding at multiple rates and by creating one or more data quality metrics for each decoded data packet. Special input and output buffering is provided to isolate the decoder (50) from system timing constraints. The input buffer (48) includes selection and accumulation logic to organize code symbol data into the packet order for repeat mode or random burst mode at lower frame data rates. Decoded data packets for each of several predetermined data transfer rates are held in an output buffer (54) for about half of the decoding cycle, thereby permitting the system microprocessor to examine and select the appropriate decoded data packet. The decoder (50) also can be reconfigured to operate at any one of several predetermined convolutional encoding algorithms. The Viterbi decoder (20), implemented as a single monolithic integrated circuit, can be used in any and all of many different multiuser telecommunications channels.
摘要:
A Viterbi decoder (20) for recovering the original bit data stream that was convolutionally encoded as a code symbol stream in a Code Division Multiple Access (CDMA) mobile communication system (22). The decoder (20) simultaneously decodes at the several data rates associated with certain multirate vocoders. The decoder (20) can decode at an unknown data rate in either continuous or framed packed modes. It accomplishes this by simultaneously decoding at multiple rates and by creating one or more data quality metrics for each decoded data packet. Special input and output buffering is provided to isolate the decoder (50) from system timing constraints. The input buffer (48) includes selection and accumulation logic to organize code symbol data into the packet order for repeat mode or random burst mode at lower frame data rates. Decoded data packets for each of several predetermined data transfer rates are held in an output buffer (54) for about half of the decoding cycle, thereby permitting the system microprocessor to examine and select the appropriate decoded data packet. The decoder (50) also can be reconfigured to operate at any one of several predetermined convolutional encoding algorithms. The Viterbi decoder (20), implemented as a single monolithic integrated circuit, can be used in any and all of many different multiuser telecommunications channels.