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    CACHING MEMORY ATTRIBUTE INDICATORS WITH CACHED MEMORY DATA
    2.
    发明公开
    CACHING MEMORY ATTRIBUTE INDICATORS WITH CACHED MEMORY DATA 有权
    CACHING VON SPEICHERATTRIBUTINDIKATOREN MIT GECACHTEN SPEICHERDATEN

    公开(公告)号：EP1941375A1

    公开(公告)日：2008-07-09

    申请号：EP06846130.0

    申请日：2006-10-20

    申请人： QUALCOMM Incorporated

    发明人： BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  SMITH, Rodney, Wayne

    IPC分类号： G06F12/10

    CPC分类号： G06F12/1063 ,  G06F12/1054 ,  G06F12/145 ,  Y02D10/13

    摘要： A processing system may include a memory configured to store data in a plurality of pages, a TLB, and a memory cache including a plurality of cache lines. Each page in the memory may include a plurality of lines of memory. The memory cache may permit, when a virtual address is presented to the cache, a matching cache line to be identified from the plurality of cache lines, the matching cache line having a matching address that matches the virtual address. The memory cache may be configured to permit one or more page attributes of a page located at the matching address to be retrieved from the memory cache and not from the TLB, by further storing in each one of the cache lines a page attribute of the line of data stored in the cache line.

    摘要翻译： 处理系统可以包括被配置为在多个页面中存储数据的存储器，TLB和包括多个高速缓存行的存储器高速缓存。 存储器中的每个页面可以包括多行存储器。 当将虚拟地址呈现给高速缓存时，存储器高速缓存可以允许要从多条高速缓存行识别的匹配高速缓存行，匹配高速缓存线具有与虚拟地址匹配的匹配地址。 存储器高速缓存可以被配置为通过进一步在高速缓存行的每一个中存储行的页面属性来允许位于匹配地址的页面的一个或多个页面属性从存储器高速缓存而不是从TLB检索， 的数据存储在缓存行中。

    METHOD AND APPARATUS FOR MANAGING A RETURN STACK
    5.
    发明公开
    METHOD AND APPARATUS FOR MANAGING A RETURN STACK 有权
    方法和装置返回堆栈的管理

    公开(公告)号：EP1853995A2

    公开(公告)日：2007-11-14

    申请号：EP06735437.3

    申请日：2006-02-17

    申请人： Qualcomm Incorporated

    发明人： SMITH, Rodney, Wayne ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew

    IPC分类号： G06F9/38 ,  G06F9/42

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4486

    摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.

    A METHOD AND APPARATUS FOR PREDICTING BRANCH INSTRUCTIONS
    6.
    发明授权
    A METHOD AND APPARATUS FOR PREDICTING BRANCH INSTRUCTIONS 有权

    公开(公告)号：EP1889152B1

    公开(公告)日：2018-10-10

    申请号：EP06760424.9

    申请日：2006-05-24

    申请人： QUALCOMM INCORPORATED

    发明人： SARTORIUS, Thomas, Andrew ,  STEMPEL, Brian, Michael ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SMITH, Rodney, Wayne

    IPC分类号： G06F9/38

    CPC分类号： G06F9/3844

    摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.

    METHOD AND APPARATUS FOR MANAGING A RETURN STACK
    10.
    发明授权
    METHOD AND APPARATUS FOR MANAGING A RETURN STACK 有权
    方法和装置返回堆栈的管理

    公开(公告)号：EP1853995B1

    公开(公告)日：2010-08-04

    申请号：EP06735437.3

    申请日：2006-02-17

    申请人： Qualcomm Incorporated

    发明人： SMITH, Rodney, Wayne ,  BRIDGES, Jeffrey, Todd ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew

    IPC分类号： G06F9/38 ,  G06F9/42

    CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/4486

    摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.