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    ACCESSING DATA IN MULTI-DIMENSIONAL TENSORS
    4.
    发明公开
    ACCESSING DATA IN MULTI-DIMENSIONAL TENSORS 审中-公开
    在多维张量中访问数据

    公开(公告)号：EP3226121A2

    公开(公告)日：2017-10-04

    申请号：EP16207511.3

    申请日：2016-12-30

    申请人： Google Inc.

    发明人： Woo, Dong Hyuk ,  Phelps, Andrew Everett

    IPC分类号： G06F9/30 ,  G06F9/355

    CPC分类号： G06F9/355 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/30054 ,  G06F9/30061 ,  G06F9/30065 ,  G06F9/30101 ,  G06F9/325 ,  G06F9/3455 ,  G06F9/3555 ,  G06F9/3836 ,  G06F17/16 ,  G06F2212/454

    摘要： Methods, systems, and apparatus, including an apparatus for processing an instruction for accessing a N -dimensional tensor, the apparatus including multiple tensor index elements and multiple dimension multiplier elements, where each of the dimension multiplier elements has a corresponding tensor index element. The apparatus includes one or more processors configured to obtain an instruction to access a particular element of a N -dimensional tensor, where the N -dimensional tensor has multiple elements arranged across each of the N dimensions, and where N is an integer that is equal to or greater than one; determine, using one or more tensor index elements of the multiple tensor index elements and one or more dimension multiplier elements of the multiple dimension multiplier elements, an address of the particular element; and output data indicating the determined address for accessing the particular element of the N -dimensional tensor.

    摘要翻译： 包括用于处理用于访问N维张量的指令的装置的方法，系统和装置，所述装置包括多个张量索引元素和多维度乘数元素，其中每个维度乘数元素具有对应的张量索引元素。 该设备包括一个或多个处理器，其被配置为获得访问N维张量的特定元素的指令，其中N维张量具有跨N个维度中的每一个布置的多个元素，并且其中N是等于 大于或等于1; 使用所述多个张量索引元素中的一个或多个张量索引元素和所述多维度倍数元素中的一个或多个维度倍数元素来确定所述特定元素的地址; 并输出表示用于访问N维张量的特定元素的确定地址的数据。

    SELECTING SUBROUTINE RETURN MECHANISMS
    8.
    发明授权
    SELECTING SUBROUTINE RETURN MECHANISMS 有权
    选择子程序返回机制

    公开(公告)号：EP1872203B1

    公开(公告)日：2009-04-01

    申请号：EP06701653.5

    申请日：2006-02-01

    申请人： ARM Limited

    发明人： GRISENTHWAITE, Richard Roy ,  KIMELMAN, Paul ,  SEAL, David James

    IPC分类号： G06F9/42 ,  G06F9/32

    CPC分类号： G06F9/3016 ,  G06F9/30054 ,  G06F9/322 ,  G06F9/4486

    摘要： Following execution of a subroutine, a return instruction is executed having an address as an input operand thereto. This input operand is compared with one or more predetermined values to detect a match and the return instruction response is selected in dependence upon whether or not a match is detected. Thus, the return address value can be used to invoke differing return instruction responses, such as an exception return response or a procedure return response. The one or more predetermined addresses may be conveniently allocated to the highest memory addresses within the memory map.

    COLLAPSIBLE FRONT-END TRANSLATION FOR INSTRUCTION FETCH
    9.
    发明公开
    COLLAPSIBLE FRONT-END TRANSLATION FOR INSTRUCTION FETCH 有权
    FALTBARES FRONT-END-GETRIEBE ZUM ABRUF VON INSTRUKTIONEN

    公开(公告)号：EP1994471A2

    公开(公告)日：2008-11-26

    申请号：EP07762866.7

    申请日：2007-02-01

    申请人： SUN MICROSYSTEMS, INC.

    发明人： CAPRIOLI, Paul ,  CHAUDHRY, Shailender

    IPC分类号： G06F12/10 ,  G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/3804 ,  G06F9/30054 ,  G06F12/0875 ,  G06F12/10 ,  G06F2212/655 ,  Y02D10/13

    摘要： Address translation for instruction fetching can be obviated for sequences of instruction instances that reside on a same page. Obviating address translation reduces power consumption and increases pipeline efficiency since accessing of an address translation buffer can be avoided. Certain events, such as branch mis-predictions and exceptions, can be designated as page boundary crossing events. In addition, carry over at a particular bit position when computing a branch target or a next instruction instance fetch target can also be designated as a page boundary crossing event. An address translation buffer is accessed to translate an address representation of a first instruction instance. However, until a page boundary crossing event occurs, the address representations of subsequent instruction instances are not translated. Instead, the translated portion of the address representation for the first instruction instance is recycled for the subsequent instruction instances.

    摘要翻译： 对于驻留在同一页面上的指令实例的序列，可以避免用于指令获取的地址转换。 由于可以避免地址转换缓冲区的访问，所以避免地址转换降低功耗并提高管道效率。 某些事件，如分支错误预测和例外，可以被指定为页边界交叉事件。 此外，当计算分支目标或下一指令实例获取目标时，在特定位位置进位也可以被指定为页边界交叉事件。 访问地址转换缓冲器以转换第一指令实例的地址表示。 然而，直到发生页边界交叉事件，后续指令实例的地址表示不被转换。 相反，第一个指令实例的地址表示的转换部分被循环用于后续指令实例。

    TRANSLATION LOOKASIDE BUFFER (TLB) SUPPRESSION FOR INTRA-PAGE PROGRAM COUNTER RELATIVE OR ABSOLUTE ADDRESS BRANCH INSTRUCTIONS
    10.
    发明公开
    TRANSLATION LOOKASIDE BUFFER (TLB) SUPPRESSION FOR INTRA-PAGE PROGRAM COUNTER RELATIVE OR ABSOLUTE ADDRESS BRANCH INSTRUCTIONS 审中-公开
    翻译后备缓冲器（TLB）FOR命令计数器相对或绝对地址跳转指令中的一个边减速

    公开(公告)号：EP1836561A1

    公开(公告)日：2007-09-26

    申请号：EP05849255.4

    申请日：2005-11-17

    申请人： QUALCOMM INCORPORATED

    发明人： DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STEMPEL, Brian Michael

    IPC分类号： G06F9/32 ,  G06F1/32 ,  G06F12/10

    CPC分类号： G06F12/1027 ,  G06F9/30054 ,  G06F9/32 ,  G06F9/3804 ,  G06F9/382 ,  G06F2212/1028 ,  G06F2212/655 ,  Y02D10/13

    摘要： In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.

    摘要翻译： 在流水线处理器，预解码器预先指令高速缓存的计算的PC相对和绝对地址的转移指令的分支目标地址（BTA）。 预解码器比较BTA与分支指令地址（BIA），以确定是否矿目标和指令是在同一个存储器页面。 分支目标相同的页面（BTSP）位，表明这是写入缓存和与指令相关联。 当分支执行和评估的考虑，一个TLB访问权限检查属性的BTA是，如果BTA是在同一页BIA，抑制由BTSP位所示。 这降低了功耗为TLB存取被抑制，BTA / BIA比较只执行一次，当分支指令是第一取出。 另外，该预解码器中删除从所述BTA发生和选择关键路径的BTA / BIA比较。