公开(公告)号：EP1880299A2

公开(公告)日：2008-01-23

申请号：EP06752441.3

申请日：2006-05-08

申请人： Qualcomm, Incorporated

发明人： DOCKSER, Kenneth, Alan ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  CLANCY, Robert, Douglas ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F13/38

CPC分类号： G06F13/4059 ,  G06F5/06 ,  G06F2205/126

摘要： Data from a source domain (311 ) operating at a first data rate is transferred to a FIFO (319) in another domain (313) operating at a different data rate. The FIFO (319) buffers data before transfer to a sink for further processing or storage. A source side counter (325) tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter (325) decrements in response to a data ready signal from the source domain (311)1 without delay. The counter (325) increments in response to signaling from the sink domain (313) of a read of data off the FIFO (319). Hence, incrementing is subject to the signaling latency between domains. The source (315) may send one more beat of data when the counter (325) indicates the FIFO (319) is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one o more FIFO positions.

公开(公告)号：EP1849062A2

公开(公告)日：2007-10-31

申请号：EP06736336.6

申请日：2006-02-03

申请人： Qualcomm Incorporated

发明人： BRIDGES, Jeffrey, Todd ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris ,  SARTORIUS, Thomas, Andrew

IPC分类号： G06F9/312

CPC分类号： G06F9/30043

摘要： One or more architected registers in a processor are fractional-word writable, and data from plural misaligned memory access operations are assembled directly in an architected register, without first assembling the data in a fractional-word writable, non-architected register and then transferring it to the architected register. In embodiments where a general-purpose register file utilizes register renaming or a reorder buffer, data from plural misaligned memory access operations are assembled directly in a fractional-word writable architected register, without the need to fully exception check both misaligned memory access operations before performing the first memory access operation.

公开(公告)号：EP1869557B1

公开(公告)日：2017-09-27

申请号：EP06739774.5

申请日：2006-03-23

申请人： QUALCOMM INCORPORATED

发明人： SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris

IPC分类号： G06F12/08 ,  G06F12/0804

CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

摘要翻译： 处理器包括具有根据回拷算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示缓存中的任何回拷条目是否包含修改后的数据。 在高速缓存未命中时，如果GMI指示高速缓存中没有任何回拷条目包含修改后的数据，则从内存中取回的数据将被写入所选条目，而无需先读取条目。 在银行缓存中，两个或更多银行GMI可能与两个或更多银行相关联。 在n路组关联高速缓存中，n个集合GMI可以与n个集合相关联。 抑制读取以确定回拷缓存条目是否包含修改的数据可提高处理器性能并降低功耗。

公开(公告)号：EP1934754A1

公开(公告)日：2008-06-25

申请号：EP06815156.2

申请日：2006-09-21

申请人： Qualcomm Incorporated

发明人： STEMPEL, Brian, Michael ,  DIEFFENDERFER, James, Norris ,  BRIDGES, Jeffrey, Todd ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne ,  CLANCY, Robert, Douglas ,  AUGSBURG, Victor, Roberts

IPC分类号： G06F12/12

CPC分类号： G06F12/126

摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.

公开(公告)号：EP1869557A2

公开(公告)日：2007-12-26

申请号：EP06739774.5

申请日：2006-03-23

申请人： QUALCOMM INCORPORATED

发明人： SARTORIUS, Thomas, Andrew ,  AUGSBURG, Victor, Roberts ,  DIEFFENDERFER, James, Norris

IPC分类号： G06F12/08

CPC分类号： G06F12/0804 ,  G06F2212/1028 ,  Y02D10/13

摘要： A processor includes a cache memory having at least one entry managed according to a copy-back algorithm. A global modified indicator (GMI) indicates whether any copy-back entry in the cache contains modified data. On a cache miss, if the GMI indicates that no copy-back entry in the cache contains modified data, data fetched from memory are written to the selected entry without first reading the entry. In a banked cache, two or more bank-GMIs may be associated with two or more banks. In an n-way set associative cache, n set-GMIs may be associated with the n sets. Suppressing the read to determine if the copy-back cache entry contains modified data improves processor performance and reduces power consumption.

摘要翻译： 处理器包括具有根据回写算法管理的至少一个条目的高速缓冲存储器。 全局修改指示符（GMI）指示高速缓存中的任何复制条目是否包含修改的数据。 在缓存未命中时，如果GMI指示高速缓存中没有复制条目包含修改的数据，则从内存中读取的数据将被写入所选条目，而无需先阅读条目。 在银行缓存中，两个或更多个银行GMI可以与两个或更多个银行相关联。 在n路集合关联高速缓存中，n个集合GMI可以与n个集合相关联。 禁止读取以确定复制缓存条目是否包含修改的数据是否提高了处理器性能并降低了功耗。