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    FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA
    1.
    发明公开
    FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 有权
    FUSION条件写入在指令处理电路和相反条件的处理器系统，方法和计算机可读媒体指令

    公开(公告)号：EP2850515A1

    公开(公告)日：2015-03-25

    申请号：EP13724143.6

    申请日：2013-05-16

    申请人： Qualcomm Incorporated

    发明人： BROWN, Melinda J. ,  DIEFFENDERFER, James Norris ,  MCILVAINE, Michael Scott ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne ,  SCHOTTMILLER, Jeffery M. ,  IRWIN, Andrew S. ,  MORROW, Michael William

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3017

    摘要： Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

    摘要翻译： 熔合具有指令处理电路和相关的处理器的系统，方法，和计算机可读介质相反条件的有条件写入指令是游离缺失盘。 在一个实施方式中，写入基于评估第一条件的第一值到目标寄存器的第一有条件写入指令是通过在指令处理电路检测到。 因此，该电路检测第二有条件写入指令写入基于评估第二条件做了第二值到目标寄存器在第一条件的逻辑相反。 所述第一条件或第二条件被选择为稠合的指令条件，和相应的值被选择为，如果为真，并且如果假值。 为如果真值选择性地写入到目标寄存器，如果融合指令条件评估为真，并且选择性地将如果假值写入到目标寄存器，如果融合指令条件评估为假时产生的融合指令。