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    FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA
    2.
    发明公开
    FUSING CONDITIONAL WRITE INSTRUCTIONS HAVING OPPOSITE CONDITIONS IN INSTRUCTION PROCESSING CIRCUITS, AND RELATED PROCESSOR SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA 有权
    FUSION条件写入在指令处理电路和相反条件的处理器系统，方法和计算机可读媒体指令

    公开(公告)号：EP2850515A1

    公开(公告)日：2015-03-25

    申请号：EP13724143.6

    申请日：2013-05-16

    申请人： Qualcomm Incorporated

    发明人： BROWN, Melinda J. ,  DIEFFENDERFER, James Norris ,  MCILVAINE, Michael Scott ,  STEMPEL, Brian Michael ,  SMITH, Rodney Wayne ,  SCHOTTMILLER, Jeffery M. ,  IRWIN, Andrew S. ,  MORROW, Michael William

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3867 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/3017

    摘要： Fusing conditional write instructions having opposite conditions in instruction processing circuits and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first conditional write instruction writing a first value to a target register based on evaluating a first condition is detected by an instruction processing circuit. The circuit also detects a second conditional write instruction writing a second value to the target register based on evaluating a second condition that is a logical opposite of the first condition. Either the first condition or the second condition is selected as a fused instruction condition, and corresponding values are selected as if-true and if-false values. A fused instruction is generated for selectively writing the if-true value to the target register if the fused instruction condition evaluates to true, and selectively writing the if-false value to the target register if the fused instruction condition evaluates to false.

    摘要翻译： 熔合具有指令处理电路和相关的处理器的系统，方法，和计算机可读介质相反条件的有条件写入指令是游离缺失盘。 在一个实施方式中，写入基于评估第一条件的第一值到目标寄存器的第一有条件写入指令是通过在指令处理电路检测到。 因此，该电路检测第二有条件写入指令写入基于评估第二条件做了第二值到目标寄存器在第一条件的逻辑相反。 所述第一条件或第二条件被选择为稠合的指令条件，和相应的值被选择为，如果为真，并且如果假值。 为如果真值选择性地写入到目标寄存器，如果融合指令条件评估为真，并且选择性地将如果假值写入到目标寄存器，如果融合指令条件评估为假时产生的融合指令。

    METHODS AND APPARATUS FOR ISSUING MEMORY BARRIER COMMANDS IN A WEAKLY ORDERED STORAGE SYSTEM
    3.
    发明公开
    METHODS AND APPARATUS FOR ISSUING MEMORY BARRIER COMMANDS IN A WEAKLY ORDERED STORAGE SYSTEM 有权
    刊发的内存屏障的方法和设备命令在具有弱势整理的存储系统

    公开(公告)号：EP2435919A1

    公开(公告)日：2012-04-04

    申请号：EP10722474.3

    申请日：2010-05-26

    申请人： QUALCOMM Incorporated

    发明人： SPEIER, Thomas Philip ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1621 ,  G06F12/0811 ,  G06F12/0835

    摘要： Efficient techniques are described for enforcing order of memory accesses. A memory access request is received from a device which is not configured to generate memory barrier commands. A surrogate barrier is generated in response to the memory access request. A memory access request may be a read request. In the case of a memory write request, the surrogate barrier is generated before the write request is processed. The surrogate barrier may also be generated in response to a memory read request conditional on a preceding write request to the same address as the read request. Coherency is enforced within a hierarchical memory system as if a memory barrier command was received from the device which does not produce memory barrier commands.

    摘要翻译： 有效的技术被描述为执行顺序的存储器存取。 一个存储器存取请求是从一个设备接收到的所有未配置为产生存储器屏障命令。 甲代孕屏障是响应于存储器访问请求生成。 一个存储器存取请求可以是一个读请求。 在存储器中的写请求的情况下，被处理的写请求之前生成所述替代阻挡层。 替代屏障可因此响应于存储器读取请求上的preceding-写入请求相同的地址作为读出请求的条件来生成。 相干性分级存储器系统内强制执行，犹如从不产生存储器屏障命令装置接收到的存储器屏障命令。

    METHODS AND APPARATUS FOR LOW-COMPLEXITY INSTRUCTION PREFETCH SYSTEM
    4.
    发明授权
    METHODS AND APPARATUS FOR LOW-COMPLEXITY INSTRUCTION PREFETCH SYSTEM 有权
    方法和设备对于命令ADVANCE充电系统低复杂度

    公开(公告)号：EP2097809B1

    公开(公告)日：2011-06-15

    申请号：EP07865095.9

    申请日：2007-12-03

    申请人： QUALCOMM Incorporated

    发明人： MORROW, Michael William ,  DIEFFENDERFER, James Norris

    IPC分类号： G06F9/38 ,  G06F12/08

    CPC分类号： G06F9/3802 ,  G06F12/0862

    摘要： When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X% into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.

    SNOOP FILTERING USING A SNOOP REQUEST CACHE
    5.
    发明公开
    SNOOP FILTERING USING A SNOOP REQUEST CACHE 审中-公开
    SNOOP滤波用缓冲FOR SNOOP要求

    公开(公告)号：EP2115597A1

    公开(公告)日：2009-11-11

    申请号：EP08728411.3

    申请日：2008-01-28

    申请人： QUALCOMM Incorporated

    发明人： DIEFFENDERFER, James Norris

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831

    摘要： A snoop request cache maintains records of previously issued snoop requests. Upon writing shared data, a snooping entity performs a lookup in the cache. If the lookup hits (and, in some embodiments, includes an identification of a target processor) the snooping entity suppresses the snoop request. If the lookup misses (or hits but the hitting entry lacks an identification of the target processor) the snooping entity allocates an entry in the cache (or sets an identification of the target processor) and directs a snoop request such to the target processor, to change the state of a corresponding line in the processor's L1 cache. When the processor reads shared data, it performs a snoop cache request lookup, and invalidates a hitting entry in the event of a hit (or clears it processor identification from the hitting entry), so that other snooping entities will not suppress snoop requests to it.

    SEGMENTED PIPELINE FLUSHING FOR MISPREDICTED BRANCHES
    6.
    发明公开
    SEGMENTED PIPELINE FLUSHING FOR MISPREDICTED BRANCHES 有权
    基于分段流水线处理虚假PREDICTED分枝

    公开(公告)号：EP2115572A1

    公开(公告)日：2009-11-11

    申请号：EP08713995.2

    申请日：2008-01-24

    申请人： Qualcomm Incorporated

    发明人： MCILVAINE, Michael Scott ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/384 ,  G06F9/3842 ,  G06F9/3863 ,  G06F9/3867

    摘要： A processor pipeline is segmented into an upper portion - prior to instructions going out of program order - and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.

    POWER SAVING METHODS AND APPARATUS FOR VARIABLE LENGTH INSTRUCTIONS
    8.
    发明公开
    POWER SAVING METHODS AND APPARATUS FOR VARIABLE LENGTH INSTRUCTIONS 有权
    节能方法和设备指令的变量长度

    公开(公告)号：EP1904922A2

    公开(公告)日：2008-04-02

    申请号：EP06736989.2

    申请日：2006-03-03

    申请人： QUALCOMM INCORPORATED

    发明人： STEMPEL, Brian Michael ,  DIEFFENDERFER, James Norris ,  BRIDGES, Jeffrey Todd ,  SMITH, Rodney Wayne ,  SARTORIUS, Thomas Andrew

    IPC分类号： G06F9/30

    CPC分类号： G06F9/382 ,  G06F9/30152 ,  G06F9/3816 ,  G06F12/0875 ,  Y02D10/13

    摘要： A processor capable of fetching and executing variable length instructions is described having instructions of at least two lengths. The processor operates in multiple modes. One of the modes restricts instructions that can be fetched and executed to the longer length instructions. An instruction cache is used for storing variable length instructions and their associated predecode bit fields in an instruction cache line and storing the instruction address and processor operating mode state information at the time of the fetch in a tag line. The processor operating mode state information indicates the program specified mode of operation of the processor. The processor fetches instructions from the instruction cache for execution. As a result of an instruction fetch operation, the instruction cache may selectively enable the writing of predecode bit fields in the instruction cache and may selectively enable the reading of predecode bit fields stored in the instruction cache based on the processor state at the time of the fetch.