摘要:
Various embodiments of methods and systems for energy efficiency aware thermal management in a portable computing device that contains a heterogeneous, multi-processor system on a chip (“SoC”) are disclosed. Because individual processing components in a heterogeneous, multi-processor SoC may exhibit different processing efficiencies at a given temperature, energy efficiency aware thermal management techniques that compare performance data of the individual processing components at their measured operating temperatures can be leveraged to optimize quality of service (“QoS”) by adjusting the power supplies to, reallocating workloads away from, or transitioning the power mode of, the least energy efficient processing components. In these ways, embodiments of the solution optimize the average amount of power consumed across the SoC to process a MIPS of workload.
摘要:
Systems, methods, and computer programs are disclosed for reducing leakage power of a system on chip (SoC). One such method comprises monitoring a plurality of temperature differentials across a respective plurality of thermoelectric coolers on a system on chip (SoC). Each of the thermoelectric coolers is dedicated to a corresponding one of a plurality of chip sections on the SoC. The thermoelectric coolers are controlled based on the plurality of temperature differentials to minimize a sum of a combined power consumption of the plurality of chip sections and the plurality of corresponding dedicated thermoelectric coolers.
摘要:
A method and system for optimizing a core voltage level of a portable computing device ("PCD") and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values for a plurality of subsystems is determined. At least one subsystem is a multiplexed subsystem. Next, a reduced set of voltage values is calculated based on the plurality of voltage values and an optimized voltage level is determined for a shared power domain. The shared power domain is subsequently set to the optimized voltage level. If the optimized voltage level is determined to exceed a required voltage level for the at least one multiplexed subsystem when it is running the plurality of processing engines, a subset of the plurality of processing engines may be identified to process a workload of the multiplexed system at a more efficient level of power consumption than the full plurality of processing engines.
摘要:
A method and system for optimizing a core voltage level of a portable computing device (“PCD”) and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.
摘要:
A method and system for optimizing a core voltage level of a portable computing device ("PCD") and enhancing frequency performance of individual subcomponents are disclosed. A plurality of voltage values is determined for a plurality of subcomponents within the PCD. Next, a reduced set of voltage values may be calculated with a voltage aggregator based on the plurality of voltage values. An optimized voltage level for a shared power domain may then be determined by a voltage optimizer within the PCD from the reduced set of voltage values. A shared power domain may then be set to the optimized voltage level. Subsequently, an operating frequency of each subcomponent may be optimized with a frequency performance enhancer based on the optimized voltage level. An optimal power collapse duration may also be calculated by the frequency performance enhancer and set for each subcomponent from the optimal frequency.