DELAY CIRCUITS MATCHING DELAYS OF SYNCHRONOUS CIRCUITS
    2.
    发明公开
    DELAY CIRCUITS MATCHING DELAYS OF SYNCHRONOUS CIRCUITS 审中-公开
    MITVERZÖGERUNGENSYNCHRONER SCHALTUNGENÜBEREINSTIMMENDEVERZÖGERUNGSSCHALTUNGEN

    公开(公告)号:EP2212996A1

    公开(公告)日:2010-08-04

    申请号:EP08833259.8

    申请日:2008-09-23

    IPC分类号: H03K3/037

    CPC分类号: H03K3/037

    摘要: Delay circuits capable of providing delays closely matching propagation delays of synchronous circuits are described. In one design, an apparatus includes a synchronous circuit and a delay circuit. The synchronous circuit includes a forward path from a data input to a data output. The synchronous circuit receives input data and provides output data with a propagation delay. The delay circuit receives an input signal and provides a delayed input signal having a delay matching the propagation delay of the synchronous circuit. The delay circuit includes at least two logic gates in the forward path of the synchronous circuit. The synchronous and delay circuits may be implemented based on the same or similar circuit architecture. The delay circuit may be based on a replica of the synchronous circuit, with the replica having feedback loops broken and clock input coupled to appropriate logic value to always enable the delay circuit.

    摘要翻译: 描述了能够提供紧密匹配同步电路的传播延迟的延迟的延迟电路。 在一种设计中,装置包括同步电路和延迟电路。 同步电路包括从数据输入到数据输出的前向路径。 同步电路接收输入数据并提供具有传播延迟的输出数据。 延迟电路接收输入信号并提供具有与同步电路的传播延迟匹配的延迟的延迟输入信号。 延迟电路在同步电路的正向通路中包括至少两个逻辑门。 同步和延迟电路可以基于相同或类似的电路架构来实现。 延迟电路可以基于同步电路的副本,其中复制品具有反馈回路断开,并且时钟输入耦合到适当的逻辑值以总是使能延迟电路。

    LOW-POWER TOUCH SCREEN CONTROLLER
    6.
    发明公开
    LOW-POWER TOUCH SCREEN CONTROLLER 审中-公开
    低功耗触摸屏控制

    公开(公告)号:EP2277101A2

    公开(公告)日:2011-01-26

    申请号:EP09728094.5

    申请日:2009-04-03

    发明人: KESKIN, Mustafa

    IPC分类号: G06F3/041

    摘要: While taking X-Y coordinate measurements to determine the location of a point of contact on a touch screen, a controller circuit drives the touch screen with a selectable voltage. Voltages output from the touch screen are converted by an ADC into the X-coordinate and Y-coordinate values. The ADC has a convertible input voltage range. If only a low touch screen detection resolution is required, then the voltage with which the touch screen is driven is made to be substantially less than the convertible input voltage range. Only a portion of the convertible input range is usable, but this is adequate for the application and power consumption is reduced. If a higher touch screen detection resolution is required, then the touch screen is driven with a higher voltage. Power consumption is increased, but more or all of the convertible input voltage range of the ADC is then usable.

    CAMERA ZOOM BASED ON SENSOR DATA
    8.
    发明公开

    公开(公告)号:EP3335414A1

    公开(公告)日:2018-06-20

    申请号:EP16750295.4

    申请日:2016-07-14

    IPC分类号: H04N5/232 G03B5/00

    摘要: A method, an apparatus, and a computer program product for a camera zoom function are provided. The method includes associating a camera zoom with at least one sensor, detecting a physical characteristic of the camera with the at least one sensor, and adjusting the camera zoom based on the detected physical characteristic of the camera. The detecting the physical characteristic and the adjusting the camera zoom are continuous. An apparatus is provided and includes a camera, a memory, and at least one processor coupled to the memory. The at least one processor is configured to associate a camera zoom with at least one sensor, detect a physical characteristic of the camera with the at least one sensor, and adjust the camera zoom based on the detected physical characteristic of the camera. The detecting the physical characteristic and the adjusting the camera zoom are continuous.

    PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION
    9.
    发明公开
    PROGRAMMABLE DELAY CIRCUIT WITH INTEGER AND FRACTIONAL TIME RESOLUTION 审中-公开
    具有整数和分段时间分辨率的可编程延迟电路

    公开(公告)号:EP3276828A1

    公开(公告)日:2018-01-31

    申请号:EP17191587.9

    申请日:2008-12-18

    IPC分类号: H03K5/131

    摘要: A programmable delay circuit capable of providing a delay with integer and fractional time resolution is described. In one exemplary design, an apparatus includes first and second (500) delay circuits. The first delay circuit provides a first delay of an integer number of time units. The second delay circuit (500) couples to the first delay circuit and provides a second delay of a fraction of one time unit. The first delay circuit may include multiple unit delay cells coupled in series. Each unit delay cell may provide a delay of one time unit when enabled. The second delay circuit (500) may have first and second paths. The first path may provide a shorter delay when selected, and the second path may provide a longer delay when selected. The second path may be coupled to at least one dummy logic gate (518) that provides extra loading to obtain the longer delay for the second path.

    摘要翻译: 描述了能够提供具有整数和分数时间分辨率的延迟的可编程延迟电路。 在一个示例性设计中,装置包括第一和第二(500)延迟电路。 第一延迟电路提供整数个时间单位的第一延迟。 第二延迟电路(500)耦合到第一延迟电路并提供一个时间单位的一部分的第二延迟。 第一延迟电路可以包括串联耦合的多个单位延迟单元。 启用时,每个单位延迟单元可以提供一个时间单位的延迟。 第二延迟电路(500)可以具有第一和第二路径。 第一路径可以在被选择时提供较短的延迟,并且第二路径在被选择时可以提供较长的延迟。 第二路径可以耦合到提供额外负载以获得第二路径的较长延迟的至少一个伪逻辑门(518)。