公开(公告)号：EP2984756A2

公开(公告)日：2016-02-17

申请号：EP14721175.9

申请日：2014-04-04

申请人： Qualcomm Incorporated

发明人： RASOULI, Seid Hadi ,  DATTA, Animesh ,  SHAH, Jay Madhukar ,  SAINT-LAURENT, Martin ,  PARKAR, Peeyush Kumar ,  BAPAT, Sachin ,  VILANGUDIPITCHAI, Ramaprasath ,  ABU-RAHMA, Mohamed Hassan ,  PATEL, Prayag Bhanubhai

IPC分类号： H03K3/356 ,  H03K3/3562

CPC分类号： H03K3/012 ,  H03K3/356008 ,  H03K3/35625

摘要： A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

摘要翻译： 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应于逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应于控制信号来控制从站级。