公开(公告)号：EP3398060B1

公开(公告)日：2020-07-29

申请号：EP16820447.7

申请日：2016-12-09

申请人： QUALCOMM Incorporated

发明人： WRIGHT, Gregory, Michael

IPC分类号： G06F9/38 ,  G06F11/14 ,  G06F11/36

公开(公告)号：EP3682334A1

公开(公告)日：2020-07-22

申请号：EP18782227.5

申请日：2018-08-20

申请人： Qualcomm Incorporated

发明人： KRISHNA, Anil ,  YI, Yongseok ,  ROTENBERG, Eric ,  KOTHINTI NARESH, Vignyan Reddy ,  WRIGHT, Gregory, Michael

IPC分类号： G06F12/123

公开(公告)号：EP3516507A1

公开(公告)日：2019-07-31

申请号：EP17761737.0

申请日：2017-08-24

申请人： Qualcomm Incorporated

发明人： KRISHNA, Anil ,  KOTHINTI NARESH, Vignyan Reddy ,  WRIGHT, Gregory, Michael

IPC分类号： G06F9/38

公开(公告)号：EP3353674A1

公开(公告)日：2018-08-01

申请号：EP16766751.8

申请日：2016-09-02

申请人： Qualcomm Incorporated

发明人： SANKARALINGAM, Karthikeyan ,  WRIGHT, Gregory, Michael

IPC分类号： G06F15/78 ,  G06F15/82 ,  G06F9/44

CPC分类号： G06F15/7867 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3897 ,  G06F9/4494 ,  G06F15/7892 ,  G06F15/825

摘要： Configuring coarse-grained reconfigurable arrays (CGRAs) for dataflow instruction block execution in block-based dataflow instruction set architectures (ISAs) is disclosed. In one aspect, a CGRA configuration circuit is provided, comprising a CGRA having an array of tiles, each of which provides a functional unit and a switch. An instruction decoding circuit of the CGRA configuration circuit maps a dataflow instruction within a dataflow instruction block to one of the tiles of the CGRA. The instruction decoding circuit decodes the dataflow instruction, and generates a function control configuration for the functional unit of the mapped tile to provide the functionality of the dataflow instruction. The instruction decoding circuit further generates switch control configurations for switches along a path of tiles within the CGRA so that an output of the functional unit of the mapped tile is routed to each tile corresponding to consumer instructions of the dataflow instruction.