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    PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR
    2.
    发明公开
    PROCESSORS, METHODS, AND SYSTEMS WITH A CONFIGURABLE SPATIAL ACCELERATOR 审中-公开

    公开(公告)号：EP3343388A1

    公开(公告)日：2018-07-04

    申请号：EP17210484.6

    申请日：2017-12-22

    申请人： Intel Corporation

    发明人： FLEMING, Kermin ,  GLOSSOP, Kent D. ,  STEELY JR., Simon C.

    IPC分类号： G06F15/82

    CPC分类号： G06F9/3016 ,  G06F13/4221 ,  G06F15/82 ,  G06F15/825 ,  Y02D10/14 ,  Y02D10/151

    摘要： Systems, methods, and apparatuses relating to a configurable spatial accelerator are described. In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements.

    DYNAMICALLY ERECTABLE COMPUTER SYSTEM
    3.
    发明公开
    DYNAMICALLY ERECTABLE COMPUTER SYSTEM 有权
    动态AUFSTELLBARES RECHNERSYSTEM

    公开(公告)号：EP2856313A2

    公开(公告)日：2015-04-08

    申请号：EP13793168.9

    申请日：2013-05-23

    申请人： Smith, Roger

    发明人： Smith, Roger

    IPC分类号： G06F9/46

    CPC分类号： G06F15/825 ,  G06F7/76 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/2002 ,  G06F12/0875 ,  G06F15/76 ,  G06F2015/765 ,  G06F2212/452

    摘要： A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain (MM domain) which includes mentor processors for mentoring the DID according to "meta information" which includes but is not limited to data, algorithms and protective rule sets. The term "mentoring" (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes.

    摘要翻译： 容错计算机系统架构包括两种类型的操作域：处理数据和指令的常规第一域（DID），以及新颖的第二域，其中包括指导者处理器，用于根据“元信息”来指导DID，包括但是是 不限于数据，算法和保护规则集。 术语“指导”（如下文所定义）是指应用和使用元信息来强制执行规则集和/或动态建立抽象和虚拟化，通过该抽象和虚拟化，DID中的资源被洗牌，尤其是效率 和故障校正。 Meta Mentor处理器通过容错导向开关创建系统和子系统，该交换机将信号路由到硬件和软件实体。 所创建的系统和子系统是不同的子体系结构和唯一配置，其可以由执行过程所定义的单独地或同时地操作。

    PROCESSORS
    8.
    发明公开
    PROCESSORS 审中-公开

    公开(公告)号：EP2153343A2

    公开(公告)日：2010-02-17

    申请号：EP08750720.8

    申请日：2008-05-30

    申请人： The University of Reading

    发明人： ANDERSON, James, Arthur, Dean, Wallace

    IPC分类号： G06F15/82

    CPC分类号： G06F15/825

    摘要： A processing apparatus comprises a plurality of processors (12), each arranged to perform an instruction, and a bus (20) arranged to carry data and control tokens between the processors. Each processor (12) is arranged, if it receives a control token via the bus, to carry out the instruction, and on carrying out the instruction, to perform an operation on the data, to identify any of the processors (12) which are to be data target processors, and to transmit output data to any identified data target processors, to identify any of the processors which are to be control target processors, and to transmit a control token to any identified control target processors.

    摘要翻译： 一种处理装置包括多个处理器（12），每个处理器被布置为执行指令，以及总线（20），被布置为在处理器之间传送数据和控制权标。 如果每个处理器（12）通过总线接收到控制令牌，则执行该指令并且在执行该指令时对数据执行操作，以识别处理器（12）中的任何处理器 成为数据目标处理器，并将输出数据发送到任何识别的数据目标处理器，识别将成为控制目标处理器的处理器中的任何处理器，并将控制令牌发送到任何识别的控制目标处理器。

    DYNAMICALLY ERECTABLE COMPUTER SYSTEM
    9.
    发明授权
    DYNAMICALLY ERECTABLE COMPUTER SYSTEM 有权

    公开(公告)号：EP2856313B1

    公开(公告)日：2018-07-11

    申请号：EP13793168.9

    申请日：2013-05-23

    申请人： Smith, Roger

    发明人： Smith, Roger

    IPC分类号： G06F11/07 ,  G06F11/14 ,  G06F11/20

    CPC分类号： G06F15/825 ,  G06F7/76 ,  G06F11/00 ,  G06F11/1484 ,  G06F11/2002 ,  G06F12/0875 ,  G06F15/76 ,  G06F2015/765 ,  G06F2212/452

    摘要： A fault-tolerant computer system architecture includes two types of operating domains: a conventional first domain (DID) that processes data and instructions, and a novel second domain (MM domain) which includes mentor processors for mentoring the DID according to “meta information” which includes but is not limited to data, algorithms and protective rule sets. The term “mentoring” (as defined herein below) refers to, among other things, applying and using meta information to enforce rule sets and/or dynamically erecting abstractions and virtualizations by which resources in the DID are shuffled around for, inter alia, efficiency and fault correction. Meta Mentor processors create systems and sub-systems by means of fault tolerant mentor switches that route signals to and from hardware and software entities. The systems and sub-systems created are distinct sub-architectures and unique configurations that may be operated as separately or concurrently as defined by the executing processes.

    DATA PROCESSING METHOD, PROCESSOR, AND DATA PROCESSING DEVICE
    10.
    发明公开
    DATA PROCESSING METHOD, PROCESSOR, AND DATA PROCESSING DEVICE 审中-公开
    日期：二月十日

    公开(公告)号：EP3128437A1

    公开(公告)日：2017-02-08

    申请号：EP15785616.2

    申请日：2015-04-02

    申请人： Huawei Technologies Co., Ltd.

    发明人： LI, Nan ,  WANG, Linchun ,  CHEN, Hongfei

    IPC分类号： G06F15/163 ,  G06F9/38

    CPC分类号： G06F15/80 ,  G06F9/38 ,  G06F9/3826 ,  G06F9/3828 ,  G06F13/1605 ,  G06F13/4031 ,  G06F15/163 ,  G06F15/17 ,  G06F15/825 ,  G06F2207/3868

    摘要： Disclosed are a data processing method, a processor, and a data processing device. The method comprises: an arbiter sends data D (a,1) to a first processing circuit; the first processing circuit processes the data D (a,1) to obtain data D (1,2) , the first processing circuit being a processing circuit among m processing circuits; the first processing circuit sends the data D (1,2) to a second processing circuit; the second processing circuit to an m th processing circuit separately process the received data; and the arbiter receives data D (m,a) sent by the m th processing circuit. The arbiter and the m processing circuits are components of the processor. The processor further comprises an (m+1) th processing circuit. Each processing circuit in the first processing circuit to the (m+1) th processing circuit can receive first data to be processed sent by the arbiter, and process the first data to be processed. The scheme is helpful to improve efficiency of data processing.

    摘要翻译： 公开了一种数据处理方法，处理器和数据处理装置。 该方法包括：仲裁器将数据D（a，1）发送到第一处理电路; 第一处理电路处理数据D（a，1）以获得数据D（1,2），第一处理电路是m个处理电路中的处理电路; 第一处理电路将数据D（1,2）发送到第二处理电路; 第二处理电路到第m处理电路分别处理所接收的数据; 并且仲裁器接收由第m处理电路发送的数据D（m，a）。 仲裁器和m处理电路是处理器的组件。 处理器还包括第（m + 1）处理电路。 到第（m + 1）处理电路的第一处理电路中的每个处理电路可以接收由仲裁器发送的待处理的第一数据，并处理第一待处理数据。 该方案有助于提高数据处理的效率。