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Patent Agency Ranking1.发明公开Simplified dual modulus divider and method of designing a phase locked loop with first and second divider circuits 审中-公开简化双模分频器和方法，用于设计具有第一和第二分频电路锁相环
公开(公告)号：EP2757693A3
公开(公告)日：2015-07-29
申请号：EP14165273.5
申请日：2001-12-17
Applicant: Qualcomm Incorporated
Inventor： Su, David, K. , Yue, Chik, Patrick , Weber, David, J. , Zargari, Masoud
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
Abstract: The present invention provides a synthesiser having a divide circuit implemented using only a single counter along with a decoder. This allows for a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
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公开(公告)号：EP2757692B1
公开(公告)日：2016-10-12
申请号：EP14165271.9
申请日：2001-12-17
Applicant: Qualcomm Incorporated
Inventor： Su, David, K. , Yue, Chik, Patrick , Weber, David, J. , Zargari, Masoud
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
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3.发明公开Synthesizer with lock detector and method of operation thereof 有权Synthesizer mit Verriegelungsdetektor und Verfahren zum Betrieb davon
公开(公告)号：EP2757692A2
公开(公告)日：2014-07-23
申请号：EP14165271.9
申请日：2001-12-17
Applicant: Qualcomm Incorporated
Inventor： Su, David, K. , Yue, Chik, Patrick , Weber, David, J. , Zargari, Masoud
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
Abstract: The present invention provides an apparatus and method for generating a lock detect signal indicative of stability of a frequency of an output signal based upon UP and DN signals received from a phase detector. The apparatus comprises an input that receives the UP and DN signals; a first circuit that combines the received UP and DN signals to obtain a combined signal; a delay stage that operates upon the combined signal to obtain a delayed combined signal; and a second circuit that operates upon the combined signal and the delayed combined signal to obtain the lock detect signal.
Abstract translation: 本发明提供一种用于根据从相位检测器接收的UP和DN信号产生指示输出信号的频率的稳定性的锁定检测信号的装置和方法。 该装置包括接收UP和DN信号的输入端; 组合所接收的UP和DN信号以获得组合信号的第一电路; 延迟级，其对组合信号进行操作以获得延迟的组合信号; 以及第二电路，其对组合信号和延迟的组合信号进行操作以获得锁定检测信号。
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4.发明公开Synthesizer with lock detector and method of operation thereof 有权Synthesizer mit Verriegelungsdetektor und Verfahren zum Betrieb davon
公开(公告)号：EP2757692A3
公开(公告)日：2015-07-29
申请号：EP14165271.9
申请日：2001-12-17
Applicant: Qualcomm Incorporated
Inventor： Su, David, K. , Yue, Chik, Patrick , Weber, David, J. , Zargari, Masoud
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
Abstract: The present invention provides an apparatus and method for generating a lock detect signal indicative of stability of a frequency of an output signal based upon UP and DN signals received from a phase detector. The apparatus comprises an input that receives the UP and DN signals; a first circuit that combines the received UP and DN signals to obtain a combined signal; a delay stage that operates upon the combined signal to obtain a delayed combined signal; and a second circuit that operates upon the combined signal and the delayed combined signal to obtain the lock detect signal.
Abstract translation: 本发明提供了一种合成器，其具有仅使用单个计数器与解码器一起实现的除法电路。 这允许设计多个划分电路的方法，每个划分电路使用相同的单个计数器，并且每个使用不同的解码器。
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5.发明公开Simplified dual modulus divider and method of designing a phase locked loop with first and second divider circuits 审中-公开简化双模分频器和方法，用于设计具有第一和第二分频电路锁相环
公开(公告)号：EP2757693A2
公开(公告)日：2014-07-23
申请号：EP14165273.5
申请日：2001-12-17
Applicant: Qualcomm Incorporated
Inventor： Su, David, K. , Yue, Chik, Patrick , Weber, David, J. , Zargari, Masoud
CPC classification number: H03L7/099 , H03K23/667 , H03L7/089 , H03L7/095 , H03L7/10 , H03L7/193 , Y10S331/02
Abstract: The present invention provides a synthesiser having a divide circuit implemented using only a single counter along with a decoder. This allows for a method of designing a plurality of divide circuits which each use the same single counter and each use a different decoder.
Abstract translation: 本发明提供一种具有仅使用单个计数器地连同解码器实现一个除法电路合成。 这允许设计除法电路，它们每一个使用相同的单个计数器的多个方法，并且每个用一个不同的译码器。
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