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1.发明公开Television receiver having skew corrected clock 失效Fernsehempfängermit verzerrungskorrigiertem Taktsignal。
公开(公告)号：EP0550420A2
公开(公告)日：1993-07-07
申请号：EP93200689.3
申请日：1988-03-28
IPC分类号： H04N5/12
摘要： A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator (22) for producing a signal (FFOS) having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit (30) which is reset once every horizontal line. The divide-by-K circuit comprises a divide-by-m circuit connected in series with a flip-flop (50), with said divide-by-m circuit (40) being reset by a first control signal (FCS) once every horizontal line. The apparatus additionally includes means (Fig. 2/SCS) for preventing the output of the flip-flop (50) from changing while the divide-by-m circuit is reset in response to the first control signal (FCS). In accordance with another aspect of this invention, the state of the divide-by-K circuit (30) is captured (150/SES) and saved for use in a chroma demodulation apparatus (Fig. 6) just before it is reset.
摘要翻译： 数字电视接收机包括用于产生偏斜校正时钟的装置。 该装置包括一个固定频率的自由运行振荡器（22），用于产生一个信号（FFOS），该信号的频率是偏斜校正时钟信号的期望额定频率的固定整数倍K， K电路（30），每水平线复位一次。 除以K电路包括与触发器（50）串联连接的除以m电路，所述除法电路（40）由第一控制信号（FCS）每一次复位 水平线。 该装置还包括用于在响应于第一控制信号（FCS）复位除数电路时防止触发器（50）的输出改变的装置（图2 / SCS）。 根据本发明的另一方面，在除了K电路（30）被复位之前捕获（150 / SES）并保存用于色度解调装置（图6）中的状态。
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公开(公告)号：EP0550420A3
公开(公告)日：1993-08-18
申请号：EP93200689.3
申请日：1988-03-28
IPC分类号： H04N5/12
摘要： A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator (22) for producing a signal (FFOS) having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit (30) which is reset once every horizontal line. The divide-by-K circuit comprises a divide-by-m circuit connected in series with a flip-flop (50), with said divide-by-m circuit (40) being reset by a first control signal (FCS) once every horizontal line. The apparatus additionally includes means (Fig. 2/SCS) for preventing the output of the flip-flop (50) from changing while the divide-by-m circuit is reset in response to the first control signal (FCS). In accordance with another aspect of this invention, the state of the divide-by-K circuit (30) is captured (150/SES) and saved for use in a chroma demodulation apparatus (Fig. 6) just before it is reset.
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公开(公告)号：EP0285350A3
公开(公告)日：1989-04-19
申请号：EP88302727.8
申请日：1988-03-28
IPC分类号： H04N5/44
摘要： A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator (22) for producing a signal (FFOS) having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit (30) which is reset once every horizontal line. The divide-by-K circuit comprises a divide-by-m circuit connected in series with a flip-flop (50), with said divide-by-m circuit (40) being reset by a first control signal (FCS) once every horizontal line. The apparatus additionally includes means (Fig. 2/SCS) for preventing the output of the flip-flop (50) from changing while the divide-by-m circuit is reset in response to the first control signal (FCS).
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4.发明公开Television receiver having skew corrected clock 失效Fernsehempfängermit verzerrungskorrigiertem Taktsignal。
公开(公告)号：EP0285350A2
公开(公告)日：1988-10-05
申请号：EP88302727.8
申请日：1988-03-28
IPC分类号： H04N5/44
摘要： A digital TV receiver includes an apparatus for generating a skew corrected clock. The apparatus consists of a fixed frequency, free running oscillator (22) for producing a signal (FFOS) having a frequency which is a fixed integer multiple K of the desired nominal frequency of the skew-corrected clock signal, and a divide-by-K circuit (30) which is reset once every horizontal line. The divide-by-K circuit comprises a divide-by-m circuit connected in series with a flip-flop (50), with said divide-by-m circuit (40) being reset by a first control signal (FCS) once every horizontal line. The apparatus additionally includes means (Fig. 2/SCS) for preventing the output of the flip-flop (50) from changing while the divide-by-m circuit is reset in response to the first control signal (FCS).
摘要翻译： 数字电视接收机包括用于产生偏斜校正时钟的装置。 该装置包括一个固定频率的自由运行振荡器（22），用于产生一个信号（FFOS），该信号的频率是偏斜校正时钟信号的期望额定频率的固定整数倍K， K电路（30），每水平线复位一次。 除以K电路包括与触发器（50）串联连接的除以m电路，所述除法电路（40）由第一控制信号（FCS）每一次复位 水平线。 该装置还包括用于在响应于第一控制信号（FCS）复位除数电路时防止触发器（50）的输出改变的装置（图2 / SCS）。
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