公开(公告)号：EP3985872A1

公开(公告)日：2022-04-20

申请号：EP21784927.2

申请日：2021-03-04

Applicant: REEXEN TECHNOLOGY CO., LTD.

Inventor： YANG, Xiaofeng ,  YANG, Minhao ,  LIU, Hongjie

IPC: H03H11/04 ,  G10L25/84

Abstract: The present invention relates to a time division interleaving band-pass filter for use in voice activity detection, which operates at different central frequencies in respective intervals of a predetermined period of time. The band-pass filter circuitry includes multiple band-pass filtering channels sharing a common transistor circuit, bias circuit and current mirror circuit. The multiple band-pass filtering channels operate in a time division interleaving manner, which enables the sharing of the common set of band-pass filter circuitry components. Thus, the present invention allows a reduced chip area as the area does not increase proportionally with the number of filtering channels. The invention also mitigates the influence of transistor fabrication variations on the filter's central frequencies. Moreover, pulse durations t i are additionally introduced to the determination of the central frequencies, dispensing with the need for matching of current mirror circuits and transistors and resulting in higher accuracy of the band-pass filter's central frequencies. As a result, more band-pass filtering channels with different central frequencies can be included for a given frequency range.

公开(公告)号：EP4024289A1

公开(公告)日：2022-07-06

申请号：EP21868061.9

申请日：2021-03-17

Applicant: REEXEN TECHNOLOGY CO., LTD.

Inventor： YANG, Minhao ,  LIU, Hongjie

IPC: G06N3/063

Abstract: In this application, there is proposed a current integration-based in-memory spiking neural network (SNN) using charge-domain computation which is naturally compatible with working mechanisms of neurons. In the architecture according to one aspect, silicon-based SRAM cells are included in memory cells of a synaptic array, which can avoid non-idealities caused by resistive NVM materials. Additionally, a modified NVM cell is provided, which can also benefit from the in-memory SNN architecture design of this application. When SRAM cells are used as memory cells in the synaptic array, post-neuron circuits are designed accordingly so that the in-memory SNN architecture can be used in computation with multi-bit synaptic weights by combining a programmable number of columns. Further, for computation with multi-bit synaptic weights, a circuit is designed to be time-multiplexed for resource sharing, in order to achieve improved area and energy efficiency. At last, an auto-calibration circuit is also proposed, which can counteract conducting current variation caused by, among others, process, voltage, and temperature (PVT) variations and thus allows higher computing accuracy.

公开(公告)号：EP3951662A1

公开(公告)日：2022-02-09

申请号：EP21769328.2

申请日：2021-03-04

Applicant: REEXEN TECHNOLOGY CO., LTD.

Inventor： CHEN, Qiaoqiao ,  LIU, Hongjie

IPC: G06N3/063

Abstract: A method for implementing a neural network accelerator using only on-chip memory is provided. The method includes: according to a current neural network model, determining a layer having a minimum value of an output feature map in a neural network (101); determining a quantity of layers of pipeline computing (102); determining a quantity of PEs used for pipeline computing (103); applying for a PE and storing an output feature map of the last layer of pipeline computing in on-chip memory (104), releasing a PE corresponding to a layer at which pipeline computing is completed (105), and repeating the above process at a layer at which computing is to be performed until pipeline computing is completed at all layers of the entire neural network. A neural network accelerator using only on-chip memory is further provided, including a controller, a loading module, a computing array, a post processing module, a storage module, and an on-chip buffer. The neural network accelerator using only an on-chip memory has lower power consumption, a smaller area, a higher energy efficiency ratio, and real-time and scalable performance.

公开(公告)号：EP3989445A1

公开(公告)日：2022-04-27

申请号：EP21808967.0

申请日：2021-03-30

Applicant: REEXEN TECHNOLOGY CO., LTD.

Inventor： YANG, Minhao ,  LIU, Hongjie ,  MORGADO, Alonso ,  WEBB, Neil

IPC: H03M1/46 ,  H03M1/38

Abstract: The present invention relates to a mixed-signal in-memory computing sub-cell requiring only 9 transistors for 1-bit multiplication. On the basis of this, there is proposed a computing cell constructed from a plurality of such sub-cells that share a common computing capacitor and a common transistor. As a result, the average number of transistors in each sub-cell is close to 8. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors. Also proposed is a method of fully taking advantage of data sparsity to lower the ADC block's power consumption.

公开(公告)号：EP3985670A1

公开(公告)日：2022-04-20

申请号：EP21800372.1

申请日：2021-03-30

Applicant: REEXEN TECHNOLOGY CO., LTD.

Inventor： YANG, Minhao ,  LIU, Hongjie ,  MORGADO, Alonso ,  WEBB, Neil

IPC: G11C11/413

Abstract: The present invention relates to a mixed-signal in-memory computing sub-cell requiring only 9 transistors for 1-bit multiplication. On the basis of this, there is proposed a computing cell constructed from a plurality of such sub-cells that share a common computing capacitor and common transistors. As a result, the average number of transistors in each sub-cell is close to 6. Also proposed is a MAC array for performing MAC operations, which includes a plurality of the computing cells each activating the sub-cells therein in a time-multiplexed manner. Also proposed is a differential version of the MAC array with improved computation error tolerance. Also proposed is an in-memory mixed-signal computing module for digitalizing parallel analog outputs of the MAC array and for performing other tasks in the digital domain. An ADC block in the computing module makes full use of capacitors in the MAC array, thus allowing the computing module to have a reduced area and suffer from less computation errors. Also proposed is a method of fully taking advantage of data sparsity to lower the ADC block's power consumption.