DIGITAL INTERFACE BETWEEN ANALOGUE RF HARDWARE AND DIGITAL PROCESSING HARDWARE
    1.
    发明授权
    DIGITAL INTERFACE BETWEEN ANALOGUE RF HARDWARE AND DIGITAL PROCESSING HARDWARE 有权
    之间的模拟和数字处理RF硬件硬件数字接口

    公开(公告)号:EP1362431B1

    公开(公告)日:2006-05-31

    申请号:EP02712071.6

    申请日:2002-02-14

    IPC分类号: H04B1/40 H04B1/28 H04Q7/30

    CPC分类号: H04B1/0007 H04B1/28

    摘要: A digital interface between analogue RF hardware and digital processing hardware which (a) defines how the analogue RF hardware and digital processing hardware send and receive digital data to one another and (b) is open in order to decouple the design of the analogue RF hardware from the design of the digital processing hardware. The adoption of such an interface will facilitate the uptake of software defined radio (SDR), both as a design-time and run-time technology, as it enables the production of analogue/RF components independently from the digital domain hardware and software.

    PROGRAMMABLE SINGLE-CHIP DEVICE AND RELATED DEVELOPMENT ENVIRONMENT
    2.
    发明公开
    PROGRAMMABLE SINGLE-CHIP DEVICE AND RELATED DEVELOPMENT ENVIRONMENT 有权
    可编程单芯片器件及相关开发环境

    公开(公告)号:EP1290546A2

    公开(公告)日:2003-03-12

    申请号:EP01931962.3

    申请日:2001-05-25

    IPC分类号: G06F9/00

    摘要: A programmable single-chip device, comprising a programmable gate array (PGA) section, a DSP core and a RISC core. The device is ideal for prototyping and deploying low-to-moderate volume implementations of high-bandwidth algorithms, which have processing requirements split between front-end, high iteration, low-numeric-agility, "wide" loadings, middle-end, moderate iteration, high-numerical-precision loadings and back-end, low-iteration, highly conditional loadings, without the commensurate problems inherent in the custom ASIC, joint FPGA/DSP/RISC (or even direct compilation to FPGA) solutions.

    PROGRAMMABLE SINGLE-CHIP DEVICE AND RELATED DEVELOPMENT ENVIRONMENT
    3.
    发明授权
    PROGRAMMABLE SINGLE-CHIP DEVICE AND RELATED DEVELOPMENT ENVIRONMENT 有权
    可编程单芯片器件及相关开发环境

    公开(公告)号:EP1290546B1

    公开(公告)日:2004-08-11

    申请号:EP01931962.3

    申请日:2001-05-25

    IPC分类号: G06F15/78 G06F17/50

    摘要: A programmable single-chip device, comprising a programmable gate array (PGA) section, a DSP core and a RISC core. The device is ideal for prototyping and deploying low-to-moderate volume implementations of high-bandwidth algorithms, which have processing requirements split between front-end, high iteration, low-numeric-agility, "wide" loadings, middle-end, moderate iteration, high-numerical-precision loadings and back-end, low-iteration, highly conditional loadings, without the commensurate problems inherent in the custom ASIC, joint FPGA/DSP/RISC (or even direct compilation to FPGA) solutions.

    DIGITAL INTERFACE BETWEEN ANALOGUE RF HARDWARE AND DIGITAL PROCESSING HARDWARE
    4.
    发明公开
    DIGITAL INTERFACE BETWEEN ANALOGUE RF HARDWARE AND DIGITAL PROCESSING HARDWARE 有权
    之间的模拟和数字处理RF硬件硬件数字接口

    公开(公告)号:EP1362431A2

    公开(公告)日:2003-11-19

    申请号:EP02712071.6

    申请日:2002-02-14

    IPC分类号: H04B1/40 H04B1/28 H04Q7/30

    CPC分类号: H04B1/0007 H04B1/28

    摘要: A digital interface between analogue RF hardware and digital processing hardware which (a) defines how the analogue RF hardware and digital processing hardware send and receive digital data to one another and (b) is open in order to decouple the design of the analogue RF hardware from the design of the digital processing hardware. The adoption of such an interface will facilitate the uptake of software defined radio (SDR), both as a design-time and run-time technology, as it enables the production of analogue/RF components independently from the digital domain hardware and software.

    DIGITAL TRANSACTIONS FOR THE DELIVERY OF MEDIA FILES
    6.
    发明公开
    DIGITAL TRANSACTIONS FOR THE DELIVERY OF MEDIA FILES 审中-公开
    DIGITAL交易中传递媒体文件

    公开(公告)号:EP1310056A2

    公开(公告)日:2003-05-14

    申请号:EP01949649.6

    申请日:2001-07-09

    IPC分类号: H04H1/00 H04N7/167

    摘要: An incomplete/partly corrupted media file is delivered 'in the clear'; in addition, a delta file is delivered to users meeting access control criteria which, when combined with the incomplete/partly corrupted parts allows a complete and uncorrupted version of the media file to be re-constructed. The method allows, in one implementation, a secure music purchase system to operate over digital radio: for example, the start of a song when played over the radio is usually deliberately talked over and the end cut short to prevent listeners being able to record a complete copy. With the present system, this practice can continue, but listeners can also purchase the missing or corrupted sections to enable them to possess a complete and uncorrupted version for playback.