公开(公告)号：EP1618597A2

公开(公告)日：2006-01-25

申请号：EP04759335.5

申请日：2004-04-09

申请人： Rambus, Inc.

发明人： STOJANOVIC, Vladimir, M. ,  HOROWITZ, Mark, A. ,  ZERBE, Jared, L. ,  BESSIOS, Anthony ,  HO, Andrew, C., C. ,  WEI, Jason, C. ,  TSANG, Grace ,  GARLEPP, Bruno, W.

IPC分类号： H01L21/00

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： The present invention relates to a clock data recovery circuit (600) comprising a data sampling circuit (601) to generate data samples of an input data signal (D N ) response to a first clock signal (210); an edge sampling circuit (607) to generate edge samples of the input data signal in response to a second clock signal (610); and a clock recovery circuit (605) coupled to receive the edge samples and the data samples, the clock recovery circuit being configured to adjust a phase of the second clock signal according to the state of one of the edge samples upon determining that a sequence of at least three of the data samples matches at least one sample pattern of a plurality of predetermined sample patterns.

摘要翻译： 接收电路，用于接收通过电信号导体传输的信号。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路接收来自第一和第二采样电路的第一和第二采样值，并根据先前产生的采样值选择第一采样值或第二采样值作为选择的采样值输出。

公开(公告)号：EP1618597B1

公开(公告)日：2009-03-25

申请号：EP04759335.5

申请日：2004-04-09

申请人： Rambus, Inc.

发明人： STOJANOVIC, Vladimir, M. ,  HOROWITZ, Mark, A. ,  ZERBE, Jared, L. ,  BESSIOS, Anthony ,  HO, Andrew, C., C. ,  WEI, Jason, C. ,  TSANG, Grace ,  GARLEPP, Bruno, W.

IPC分类号： H04L25/06

CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

摘要： The present invention relates to a clock data recovery circuit (600) comprising a data sampling circuit (601) to generate data samples of an input data signal (D N ) response to a first clock signal (210); an edge sampling circuit (607) to generate edge samples of the input data signal in response to a second clock signal (610); and a clock recovery circuit (605) coupled to receive the edge samples and the data samples, the clock recovery circuit being configured to adjust a phase of the second clock signal according to the state of one of the edge samples upon determining that a sequence of at least three of the data samples matches at least one sample pattern of a plurality of predetermined sample patterns.

摘要翻译： 接收电路，用于接收通过电信号导体传输的信号。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路接收来自第一和第二采样电路的第一和第二采样值，并根据先前产生的采样值选择第一采样值或第二采样值作为选择的采样值输出。

公开(公告)号：EP1573992A2

公开(公告)日：2005-09-14

申请号：EP03812838.5

申请日：2003-12-09

申请人： Rambus, Inc.

发明人： STONECYPHER, William ,  BESSIOS, Anthony ,  AGARWAL, Amita

IPC分类号： H04L25/34

CPC分类号： H04L25/4915 ,  H04L25/4919

摘要： A technique for improving the quality of digital signals in a multi-level signaling system is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for improving the quality of transmitted digital signals in a multi-level signaling system wherein digital signals representing more than one bit of information may be transmitted (104) at more than two signal levels on a single transmission medium (110). The method comprises encoding (102) digital values represented by sets of N bits to provide corresponding sets of P symbols, wherein each set of P symbols is selected to eliminate full-swing transitions between successive digital signal transmissions. The method also comprises transmitting (104) the sets of P symbols.