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    METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES
    1.
    发明授权
    METHOD TO ENHANCE MIPI D-PHY LINK RATE WITH MINIMAL PHY CHANGES AND NO PROTOCOL CHANGES 有权
    通过最少的PHY更改和无协议更改来增强MIPI D-PHY链路速率的方法

    公开(公告)号：EP3053315B1

    公开(公告)日：2017-11-01

    申请号：EP14783715.7

    申请日：2014-09-22

    申请人： Qualcomm Incorporated

    发明人： SENGOKU, Shoichiro

    IPC分类号： H04L25/14 ,  H04L7/033

    CPC分类号： H04L7/0087 ,  H04L7/0008 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/04 ,  H04L25/14

    摘要： System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

    EQUIPMENT FOR FEMTOCELL TELECOMMUNICATIONS SYSTEM
    2.
    发明公开
    EQUIPMENT FOR FEMTOCELL TELECOMMUNICATIONS SYSTEM 审中-公开
    FEMTOCELL电信系统设备

    公开(公告)号：EP3145271A1

    公开(公告)日：2017-03-22

    申请号：EP16190640.9

    申请日：2011-02-24

    申请人： Telefonaktiebolaget LM Ericsson (publ)

    发明人： Arigossi, Mauro ,  Gambini, Jonathan ,  Spagnolini, Umberto

    IPC分类号： H04W84/04 ,  H04W24/02 ,  H04W88/08 ,  H04L5/14 ,  H04W72/04

    CPC分类号： H04L5/14 ,  H04L5/005 ,  H04L7/0276 ,  H04L25/03993 ,  H04L43/028 ,  H04W72/0406 ,  H04W84/045

    摘要： A bidirectional conversion apparatus for connection via an electrical conductor based transmission line to a base apparatus providing a first information signal and control signals. The bidirectional conversion apparatus is adapted to receive/transmit from/on the transmission line the first signal and the control signals; the apparatus comprises a processing module structured to process the first signal to generate a second information signal and vice versa; the second signal being adapted to be transmitted/received by an antenna device connectable to the bidirectional conversion apparatus.

    摘要翻译： 一种双向转换设备，用于经由基于导电体的传输线连接到提供第一信息信号和控制信号的基础设备。 双向转换装置适用于从传输线路上/在传输线路上传输第一信号和控制信号; 该设备包括处理模块，该处理模块被构造为处理第一信号以产生第二信息信号，反之亦然; 该第二信号适于由可连接到双向转换装置的天线装置发送/接收。

    TAKTRÜCKGEWINNUNGSEINRICHTUNG UND VERFAHREN ZUM TAKTRÜCKGEWINNEN
    4.
    发明授权
    TAKTRÜCKGEWINNUNGSEINRICHTUNG UND VERFAHREN ZUM TAKTRÜCKGEWINNEN 有权
    德克萨斯州德克萨斯州立大学

    公开(公告)号：EP2022206B1

    公开(公告)日：2012-03-14

    申请号：EP06753246.5

    申请日：2006-05-31

    申请人： SIEMENS AKTIENGESELLSCHAFT

    发明人： HOCHLEITNER, Josef ,  KARL, Harald

    IPC分类号： H04L7/027 ,  H03L7/00

    CPC分类号： H03L7/00 ,  H04L7/027 ,  H04L7/0276

    摘要： The invention relates, among other things, to a clock signal recovery device (10) with a digital data signal input (ElO) for the input of a digital data signal (DATA) and a clock signal output (TlO) for the output of a recovered clock signal (QO), wherein the digital data signal has a given nominal clock signal frequency (fn). According to the invention, the clock signal recovery device consists of a digital circuit.

    摘要翻译： 时钟信号恢复装置具有输入数字数据信号的数字数据信号和输出恢复的时钟信号的时钟信号。 数字数据信号具有给定的额定时钟信号频率。 时钟信号恢复装置是数字电路。

    Partial response receiver
    6.
    发明授权
    Partial response receiver 有权
    部分响应接收器

    公开(公告)号：EP1618597B1

    公开(公告)日：2009-03-25

    申请号：EP04759335.5

    申请日：2004-04-09

    申请人： Rambus, Inc.

    发明人： STOJANOVIC, Vladimir, M. ,  HOROWITZ, Mark, A. ,  ZERBE, Jared, L. ,  BESSIOS, Anthony ,  HO, Andrew, C., C. ,  WEI, Jason, C. ,  TSANG, Grace ,  GARLEPP, Bruno, W.

    IPC分类号： H04L25/06

    CPC分类号： H04L25/03057 ,  H04L7/0276 ,  H04L25/063 ,  H04L25/497 ,  H04L2025/03369 ,  H04L2025/03503

    摘要： The present invention relates to a clock data recovery circuit (600) comprising a data sampling circuit (601) to generate data samples of an input data signal (D N ) response to a first clock signal (210); an edge sampling circuit (607) to generate edge samples of the input data signal in response to a second clock signal (610); and a clock recovery circuit (605) coupled to receive the edge samples and the data samples, the clock recovery circuit being configured to adjust a phase of the second clock signal according to the state of one of the edge samples upon determining that a sequence of at least three of the data samples matches at least one sample pattern of a plurality of predetermined sample patterns.

    摘要翻译： 接收电路，用于接收通过电信号导体传输的信号。 第一采样电路产生指示信号是否超过第一阈值电平的第一采样值，并且第二采样电路产生指示信号是否超过第二阈值电平的第二采样值。 第一选择电路接收来自第一和第二采样电路的第一和第二采样值，并根据先前产生的采样值选择第一采样值或第二采样值作为选择的采样值输出。

    Data communication system with frequency generation in a slave unit
    7.
    发明公开
    Data communication system with frequency generation in a slave unit 审中-公开
    在einer Slave-Einheit的Datenkommunikationssystem mit Frequenzerzeugung

    公开(公告)号：EP1971069A1

    公开(公告)日：2008-09-17

    申请号：EP07005290.7

    申请日：2007-03-14

    申请人： Nec Electronics (Europe) GmbH

    发明人： Kühne, Peter ,  Laschewski, Rüdiger ,  Turski, Klaus

    IPC分类号： H04L7/04 ,  H03L7/099 ,  H04L25/02 ,  H04L12/40

    CPC分类号： H04L7/046 ,  H03L7/0995 ,  H03L7/22 ,  H03L2207/50 ,  H04L7/0276 ,  H04L7/044 ,  H04L12/40 ,  H04L25/0262 ,  H04L27/0014 ,  H04L2027/0016 ,  H04L2027/0065 ,  H04L2027/0089

    摘要： The present invention relates to a data communication system comprising a master and at least a slave unit connected to the master unit via a bus. The master unit and the slave unit are adapted to communicate with each other using a predetermined protocol, wherein each slave unit comprises an oscillator (1) to generate a slave system frequency.
    In order to avoid complicated and expensive quartz oscillators etc. the invention proposes to use in the slave unit an adjustable oscillator and a correction unit (7) to adjust the frequency of the oscillator (1) depending on information included in the protocol.
    Preferably, the oscillator (1) is a ring oscillator comprising a plurality of inverters connected in a ring.

    摘要翻译： 数据通信系统技术领域本发明涉及一种数据通信系统，该系统包括主站和至少一个通过总线连接到主单元的从单元。 主单元和从单元适于使用预定协议彼此通信，其中每个从单元包括产生从系统频率的振荡器（1）。 为了避免复杂和昂贵的石英振荡器等，本发明提出在从单元中使用可调节振荡器和校正单元（7），以根据协议中包括的信息调整振荡器（1）的频率。 优选地，振荡器（1）是包括以环形连接的多个反相器的环形振荡器。

    Instantaneous clock recovery circuit
    8.
    发明公开
    Instantaneous clock recovery circuit 审中-公开
    Schaltkreis zur sofortigenRücksetzungeiner Uhr

    公开(公告)号：EP1432169A1

    公开(公告)日：2004-06-23

    申请号：EP03023895.0

    申请日：2003-10-21

    申请人： Northrop Grumman Corporation

    发明人： Quentin, P.

    IPC分类号： H04L7/027 ,  H03K19/195

    CPC分类号： H03L7/24 ,  H03K19/195 ,  H04L7/027 ,  H04L7/0276

    摘要： A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.

    摘要翻译： 一种用于超导体系统的时钟恢复电路（10），其能够使系统时钟的相位瞬时复位而无需任何脉冲相互作用。 时钟恢复电路（10）包括长度为2T的约瑟夫逊传输线路振荡器环路（14），其中T等于一个时钟周期。 第一和第二数据输入端（16,18）用于将数据脉冲注入到振荡器回路（14）上。 脉冲发生器（24）用于将初始时钟脉冲注入到作为周期性时钟信号输出的振荡器环路（14）上。 输出抽头（12）用于从第一和第二数据输入（16,18）之一输出数据脉冲，并且在没有数据脉冲的情况下输出周期性时钟信号。 当在第一和第二输出抽头（32,34）之一上输入数据脉冲时，时钟相位被瞬间复位。

    UNEQUALIZED CLOCK DATA RECOVERY FOR SERIAL I/O RECEIVER
    10.
    发明公开
    UNEQUALIZED CLOCK DATA RECOVERY FOR SERIAL I/O RECEIVER 审中-公开
    串行I / O接收器的不完整时钟数据恢复

    公开(公告)号：EP2839582A1

    公开(公告)日：2015-02-25

    申请号：EP12874749.0

    申请日：2012-04-19

    申请人： Intel Corporation

    发明人： HE, Yun ,  SARKAR, Sanjib ,  DENG, Fei ,  SINGARAVELU, Senthil Arun ,  NAGULAPALLY, Narender ,  SHAH, Pranali

    IPC分类号： H03K19/0175 ,  H03L7/00 ,  G06F13/00

    CPC分类号： H04L25/03057 ,  G06F13/4072 ,  H04L7/0062 ,  H04L7/0079 ,  H04L7/0087 ,  H04L7/0276 ,  H04L7/033 ,  H04L7/0332 ,  H04L25/03949

    摘要： A serial input/output method and receiver include an receiver portion to receive an analog differential serial input and sample the input to provide data and error signals, an equalization feedback loop responsive to the data and error signals to adjust the receiver portion, a phase feedback mechanism separate from the equalization feedback loop to provide a phase error, and a clock data recovery block coupled to receive the phase error to perform timing recovery for the receiver portion independent of the equalization feedback to adjust the sampling.

    摘要翻译： 串行输入/输出方法和接收器包括：接收器部分，用于接收模拟差分串行输入并采样输入以提供数据和误差信号;响应于数据和误差信号来调整接收器部分的均衡反馈回路;相位反馈 与均衡反馈环路分离以提供相位误差的机构;以及时钟数据恢复块，被耦合以接收相位误差以独立于均衡反馈来执行接收机部分的定时恢复以调整采样。