DESIGN SIMULATION USING PARALLEL PROCESSORS
    1.
    发明公开
    DESIGN SIMULATION USING PARALLEL PROCESSORS 审中-公开
    设计仿真基于并行处理器

    公开(公告)号:EP2257874A2

    公开(公告)日:2010-12-08

    申请号:EP09724182.2

    申请日:2009-03-25

    IPC分类号: G06F9/45

    摘要: A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.

    EFFICIENT PARALLEL COMPUTATION OF DEPENDENCY PROBLEMS
    2.
    发明公开
    EFFICIENT PARALLEL COMPUTATION OF DEPENDENCY PROBLEMS 审中-公开
    依赖问题的高效并行计算

    公开(公告)号:EP2297647A2

    公开(公告)日:2011-03-23

    申请号:EP09794083.7

    申请日:2009-06-30

    IPC分类号: G06F15/16

    摘要: A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs - 76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.