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    CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE
    1.
    发明公开
    CACHE REPLACEMENT POLICY THAT CONSIDERS MEMORY ACCESS TYPE 审中-公开
    RICHTLINIENFÜRCACHEERSATZ UNTERBERÜCKSICHTIGUNGDES SPEICHERZUGRIFFTYPS

    公开(公告)号：EP3055775A4

    公开(公告)日：2017-07-19

    申请号：EP14891609

    申请日：2014-12-14

    申请人： VIA ALLIANCE SEMICONDUCTOR CO LTD

    发明人： HOOKER RODNEY E ,  EDDY COLIN ,  REED DOUGLAS R ,  GREER JOHN MICHAEL ,  PARKS TERRY

    IPC分类号： G06F12/08 ,  G06F9/45 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/126 ,  G06F12/127

    CPC分类号： G06F12/0864 ,  G06F8/4442 ,  G06F12/08 ,  G06F12/0862 ,  G06F12/0877 ,  G06F12/123 ,  G06F12/126 ,  G06F12/127 ,  G06F2212/1021 ,  G06F2212/604

    摘要： An associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set. Each memory access has an associated memory access type (MAT) of a plurality of predetermined MATs. Each valid storage element has an associated MAT; a mapping that includes, for each MAT, a MAT priority. In response to a memory access that misses in the array, the allocation unit: determines a most eligible way and a second most eligible way of the selected set for replacement based on a replacement policy; and replaces the second most eligible way rather than the most eligible way when the MAT priority of the most eligible way is greater than the MAT priority of the second most eligible way.

    摘要翻译： 一种关联高速缓冲存储器，包括：以N路方式排列成M组的存储元件阵列; 分配单元响应于在高速缓冲存储器中未命中的存储器访问来分配存储元件。 每个内存访问选择一个集合。 每个存储器访问具有多个预定MAT的相关存储器访问类型（MAT）。 每个有效的存储元素都有一个关联的MAT; 对每个MAT包含MAT优先级的映射。 响应于在阵列中未命中的存储器访问，分配单元：基于替换策略确定用于替换的所选集合的最合格的方式和第二最合适的方式; 并且当最符合条件的方式的MAT优先级大于第二个最合格的方式的MAT优先级时，取代第二个最合格的方式而不是最合格的方式。

    SET ASSOCIATIVE CACHE MEMORY WITH HETEROGENEOUS REPLACEMENT POLICY
    2.
    发明公开
    SET ASSOCIATIVE CACHE MEMORY WITH HETEROGENEOUS REPLACEMENT POLICY 审中-公开
    使用多种替换策略设置关联缓存内存

    公开(公告)号：EP3129890A1

    公开(公告)日：2017-02-15

    申请号：EP14891610.9

    申请日：2014-12-14

    申请人： VIA Alliance Semiconductor Co., Ltd.

    发明人： HOOKER, Rodney, E. ,  EDDY, Colin ,  REED, Douglas, R. ,  GREER, John, Michael

    IPC分类号： G06F12/16 ,  G06F12/08

    CPC分类号： G06F12/0864 ,  G06F8/4442 ,  G06F12/0846 ,  G06F12/127 ,  G06F12/128 ,  G06F2212/1021 ,  G06F2212/6032 ,  G06F2212/6082 ,  Y02D10/13

    摘要： A set associative cache memory, comprising: an array of storage elements arranged as M sets by N ways; an allocation unit that allocates the storage elements in response to memory accesses that miss in the cache memory. Each memory access selects a set; for each parcel of a plurality of parcels, a parcel specifier specifies: a subset of ways of the N ways included in the parcel. The subsets of ways of parcels associated with a selected set are mutually exclusive; a replacement scheme associated with the parcel from among a plurality of predetermined replacement schemes. For each memory access, the allocation unit: selects the parcel specifier in response to the memory access; and uses the replacement scheme associated with the parcel to allocate into the subset of ways of the selected set included in the parcel.

    摘要翻译： 一种组相关高速缓冲存储器，包括：由N路排列为M组的存储元件阵列; 分配单元，响应于在高速缓冲存储器中未命中的存储器访问而分配存储元件。 每个内存访问选择一个集合; 对于多个包裹中的每个包裹，包裹说明符指定：包含在包裹中的N个路线的子集。 与选定集相关联的地块的子集方式是相互排斥的; 从多个预定替换方案中选择与该包相关联的替换方案。 对于每个内存访问，分配单元：响应内存访问选择宗地说明符; 并使用与包裹相关联的替换方案分配到包裹中包括的选定集合的路线的子集。

    METHOD AND NODE ENTITY FOR ENHANCING CONTENT DELIVERY NETWORK
    4.
    发明公开
    METHOD AND NODE ENTITY FOR ENHANCING CONTENT DELIVERY NETWORK 有权
    VERFAHREN UND KNOTENEINHEITFÜREINLEISTUNGSSTÄRKERESINHALTSBEREITSTELLUNGSNETZWERK

    公开(公告)号：EP2532137A1

    公开(公告)日：2012-12-12

    申请号：EP10845359.8

    申请日：2010-02-05

    申请人： Telefonaktiebolaget L M Ericsson (PUBL)

    发明人： PUTHALATH, Hareesh ,  HELLKVIST, Stefan ,  KLING, Lars-Örjan

    IPC分类号： H04L29/06 ,  G06F17/30

    CPC分类号： H04L67/2842 ,  G06F8/4441 ,  G06F8/4442 ,  G06F12/08 ,  H04L67/02 ,  H04L67/1095

    摘要： The present invention provides a method and a caching node entity for ensuring at least a predetermined number of a content object to be kept stored in a network, comprising a plurality of cache nodes for storing copies of content objects. The present invention makes use of ranking states values, deletable or non-deletable, which when assigned to copies of content objects are indicating whether a copy is either deletable or non-deletable. At least one copy of each content object is assigned the value non-deletable. The value for a copy of a content object changing from deletable to non-deletable in one cache node of the network, said copy being a candidate for the value non-deletable, if a certain condition is fulfilled.

    摘要翻译： 本发明提供了一种方法和缓存节点实体，用于确保至少预定数量的要保存在网络中的内容对象，包括用于存储内容对象的副本的多个高速缓存节点。 本发明利用排序状态值，可删除或不可删除，当分配给内容对象的副本时，其指示副本是否是可删除的或不可删除的。 每个内容对象的至少一个副本被分配值不可删除。 内容对象的副本的值从网络的一个缓存节点中的可删除到不可删除的文件的值，如果满足某个条件，则该副本是该值不可删除的候选者。

    EFFICIENT PARALLEL COMPUTATION OF DEPENDENCY PROBLEMS
    6.
    发明公开
    EFFICIENT PARALLEL COMPUTATION OF DEPENDENCY PROBLEMS 审中-公开
    依赖问题的高效并行计算

    公开(公告)号：EP2297647A2

    公开(公告)日：2011-03-23

    申请号：EP09794083.7

    申请日：2009-06-30

    申请人： Rocketick Technologies Ltd

    发明人： MIZRACHI, Shay ,  TAL, Uri ,  BEN-DAVID, Tomer

    IPC分类号： G06F15/16

    CPC分类号： G06F8/456 ,  G06F8/4442 ,  G06F8/451

    摘要： A computing method includes accepting a definition of a computing task (68), which includes multiple atomic Processing Elements (PEs - 76) having execution dependencies (80). Each execution dependency specifies that a respective first PE is to be executed before a respective second PE. The computing task is compiled for concurrent execution on a multiprocessor device (32), which includes multiple processors (44) that are capable of executing a first number of the PEs simultaneously, by arranging the PEs, without violating the execution dependencies, in an invocation data structure (90) including a second number of execution sequences (98) that is greater than one but does not exceed the first number. The multiprocessor device is invoked to run software code that executes the execution sequences in parallel responsively to the invocation data structure, so as to produce a result of the computing task.

    A method for determining a storage-bandwidth optimized memory organization of an essentially digital device
    7.
    发明公开
    A method for determining a storage-bandwidth optimized memory organization of an essentially digital device 审中-公开
    一种用于确定大致数字装置的存储器带宽优化的存储器组织的方法

    公开(公告)号：EP0974898A3

    公开(公告)日：2008-12-24

    申请号：EP99202437.2

    申请日：1999-07-23

    申请人： INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM VZW

    发明人： Wuytack, Sven ,  Catthoor, Francky ,  De Man, Hugo

    IPC分类号： G06F9/46

    CPC分类号： H04N19/423 ,  G06F8/433 ,  G06F8/4442 ,  G06F17/5045 ,  G06F2217/78 ,  Y10S707/99943

    摘要： A formalized method and a design system are described for part of the design decisions, related to memory, involved while designing an essentially digital device. The method and system determine an optimized memory organization starting from a representation of said digital device, the representation describing the functionality of the digital device and comprising data access instructions on basic groups, which are groups of scalar signals. The method and system determine optimized scheduling intervals of said data access instructions such that execution of said functionality with the digital device is guaranteed to be within a predetermined cycle budget, the determining of the optimized scheduling intervals comprising optimizing access conflicts with respect to an evaluation criterion related to the memory cost of said digital device. An optimized memory organization is selected in accordance with the optimized scheduling intervals and the optimized access conflicts.

    MECHANISMS FOR DYNAMIC CONFIGURATION OF VIRTUAL PROCESSOR RESOURCES
    9.
    发明公开
    MECHANISMS FOR DYNAMIC CONFIGURATION OF VIRTUAL PROCESSOR RESOURCES 审中-公开
    机制进行动态配置虚拟处理器资源

    公开(公告)号：EP1660998A1

    公开(公告)日：2006-05-31

    申请号：EP04782455.2

    申请日：2004-08-27

    申请人： MIPS Technologies, Inc.

    发明人： KISSELL, Kevin

    IPC分类号： G06F9/46

    CPC分类号： G06F9/3009 ,  G06F8/4442 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4881 ,  G06F9/54

    摘要： The apparatus includes a virtual multiprocessor context, one or more virtual processing element contexts, and configuration logic. The virtual multiprocessor context, prescribes the resources, and controls a configuration state of the virtual multiprocessor. The one or more virtual processing element contexts each exclusively correspond to one of the one or more virtual processing elements. The one or more virtual processing element contexts each have first logic, for prescribing whether the one of the one or more virtual processing elements is permitted to configure the resources; and second logic, for prescribing a subset of the resources that is allocated to said one of the one or more virtual processing elements. The configuration logic is coupled to the virtual multiprocessor context and the one or more virtual processing element contexts. The configuration logic detects whether the one of the one or more virtual processing elements is permitted to configure the resources, updates the virtual multiprocessor context to direct that the virtual multiprocessor enter the configuration state, and configures the resources by updating a prescribed virtual processing element context.