公开(公告)号：EP2012244A1

公开(公告)日：2009-01-07

申请号：EP07111899.6

申请日：2007-07-06

申请人： Seiko Epson Corporation

发明人： López Villegas, José María ,  Tanaka, Kazuaki

IPC分类号： G06F17/50 ,  H01F5/00 ,  H01F17/02

CPC分类号： H01F17/0006 ,  G06F17/5068 ,  H01F2017/0046 ,  H01F2017/0086 ,  H01L23/5227 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention refers to a method for designing a compact size inductor, which inductor is a spiral of N turns occupying a square area of DxD, D being its outer dimension, and where s is the turn-to-turn spacing, d its inner dimension, w is the constant strip-width; the compact size inductor having an equivalent inductance L eq ; the method comprising the following steps:
obtaining a dependency of the inductance value L eq on the minimum inductor's outer dimension D min and fitting a curve using a non-linear expression;

the resulting compact size inductor is obtained, for a given inductance value L eq and considering fixed minimum values of the turn-to-turn spacing s min , the inner dimension d min and the constant strip-width w min :
- obtaining a minimum outer dimension D min using said non-linear expression;
- filling a square of D min xD min with as many turns as possible, starting from the outside inwards, taking into account the geometrical restriction defined by: N = int D min ⁢ s min ⁢ w min ⁢ d min .

摘要翻译： 本发明涉及一种方法，用于设计紧凑的尺寸电感器，其中电感器是N的螺旋圈占据DXD，D的正方形面积为它的外部尺寸，并且其中s是圈对转弯间距，d其内部尺寸 ，w是常数条宽度; 具有等效电感L当量的紧凑的尺寸电感器; 该方法包括以下步骤：获得所述最小电感的外尺寸D分钟的电感值L当量的依赖性和使用非线性表达拟合的曲线; 将所得的紧凑的尺寸电感器获得，对于给定的电感值L当量，并考虑固定导到匝间距s分钟，内尺寸d min，并且恒定带宽度w分钟的最小值： - 获得的最小外 尺寸D min，使用所述非线性表达; - 填充的ð分钟的xD分钟的方形与尽可能多的匝数成为可能，从外侧开始向内，考虑到由所限定的几何限制：N = INTð分钟¢s最小¢¢瓦特分钟ð分钟。

公开(公告)号：EP2131499A1

公开(公告)日：2009-12-09

申请号：EP08157419.6

申请日：2008-06-02

申请人： Seiko Epson Corporation

发明人： Redondo Navarro, Xavier ,  Pallarès Cuxart, Jofre ,  Serra Graells, Francesc ,  Terés Terés, Lluís ,  Cairo Molins, Josep Ignasi ,  Gil Gali, Ignacio ,  Tanaka, Kazuaki

IPC分类号： H03L7/197 ,  H03M7/00

CPC分类号： H03L7/1976 ,  H03M7/3015

摘要： The invention refers to a digital accumulator with reconfigurable resolution (10) an input signal of which has m + n bits, the digital accumulator comprises:
- a first adding means (20, 20') and a first register means (40) in series connection, said first adding means having as addends the m most-significant-bits MSB of the input signal (60) and the output (41) of the first register means,
- a second adding means (30, 30') and a second register means (50) in series connection, said second adding means having as addends the n least-significant-bits LSB of the input signal (60) and the output (51) of the second register means; and,
- input means for an enabling signal (70), which input means are connected so as to have an effect on operation of both the second adding means (30) and the second register means (50), and in response to activating said enabling signal the least-significant-bits of the input signal are set to 0 at the second adding means and the second register means are reset
The invention also refers to a sigma-delta modulator comprising at least one of such digital accumulators

摘要翻译： 本发明涉及具有可重配置分辨率（10）的数字累加器，其输入信号具有m + n位，数字累加器包括： - 第一加法装置（20,20'）和串联的第一寄存器装置（40） 所述第一加法装置具有加法器输入信号（60）的m个最高有效位MSB和第一寄存器装置的输出（41）， - 第二加法装置（30,30'）和第二加法装置 串联连接的寄存器装置（50），所述第二加法装置具有加法器输入信号（60）和第二寄存器装置的输出（51）的n个最低有效位LSB; 以及 - 用于使能信号（70）的输入装置，所述输入装置被连接以便对第二加法装置（30）和第二寄存器装置（50）两者的操作产生影响，并且响应于激活所述 使能信号，在第二加法装置将输入信号的最低有效位设置为0，并且第二寄存器装置被复位本发明还涉及一种Σ-Δ调制器，其包括至少一个这样的数字累加器

公开(公告)号：EP1496621A1

公开(公告)日：2005-01-12

申请号：EP04253828.0

申请日：2004-06-25

申请人： SEIKO EPSON CORPORATION

发明人： Watanabe, Toru ,  Takada, Yutaka ,  Inoguchi, Makoto ,  Yajima, Aritsugu ,  Tanaka, Kazuaki ,  Takagi, Shigekazu

IPC分类号： H04B1/40

CPC分类号： H04B1/006 ,  H04B1/0057 ,  H04B1/406 ,  H04B1/52

摘要： The invention seeks to provide a high-frequency composite component capable of: simplifying the circuits from the antenna to the input side of the high-frequency amplifier circuit; suppressing a loss in the signal; and reducing the cost and the size, when a wireless system using plural frequency bands, such as a wireless LAN system using plural frequencies, is constructed. The high-frequency composite component is fabricated by placing an antenna 1 on a multi-layer wiring board 41, placing a multiplexer/demultiplexer circuit 2, matching circuits 3 and 4, and balanced-to-unbalanced transformer circuits 5 and 6 inside the board 41 respectively, and providing input and output terminals 7 through 10 on the side surface of the board 41. The antenna 1 is connected to the multiplexer/demultiplexer circuit 2 via an unbalanced line path 11, and the multiplexer/demultiplexer 2 is connected to the matching circuits 3 and 4 via unbalanced line paths 12 and 13, respectively. The matching circuits 3 and 4 are connected to the balanced-to-unbalanced transformer circuits 5 and 6, respectively, via unbalanced line paths 14 and 15, respectively. The respective balanced terminals of the balanced-to-unbalanced transformer circuits 5 and 6 are connected to the input and output terminals 7 and 8, and 9 and 10, respectively, via balanced line paths 16 and 17, respectively.

摘要翻译： 本发明试图提供一种高频复合元件，其能够：简化从天线到高频放大器电路的输入侧的电路; 抑制信号中的损失; 并且当构建使用多个频带的无线系统（诸如使用多个频率的无线LAN系统）时降低成本和尺寸。 通过将天线1放置在多层布线板41上，将多路复用器/解复用器电路2，匹配电路3和4以及平衡 - 不平衡变压器电路5和6放置在电路板内部来制造高频复合元件 并在基板41的侧面上设置输入输出端子7〜10。天线1经由不平衡线路11与多路复用器/多路分离器电路2连接，多路复用器/多路分离器2与 通过不平衡线路径12和13分别匹配电路3和4。 匹配电路3和4分别通过不平衡线路径14和15分别连接到平衡 - 不平衡变压器电路5和6。 平衡 - 不平衡变压器电路5和6的各个平衡端子分别经由平衡线路径16和17连接到输入和输出端子7和8以及9和10。