公开(公告)号：EP0851470A1

公开(公告)日：1998-07-01

申请号：EP96830645.6

申请日：1996-12-24

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Sonego, Patrizia ,  Colabella, Elio ,  Bacchetta, Maurizio ,  Pividori, Luca

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/316

CPC分类号： H01L21/76819 ,  H01L21/31056 ,  H01L21/316

摘要： A plurality of bit lines (6) are isolated from one another by a layered dielectric structure to provide a planar architecture onto which an optional conductive layer may be deposited.
The dielectric structure deposited with the method proposed in the instant Patent Application uses a highly planarizing dielectric layer (18) of the SOG type spun over a first insulating dielectric layer (17) and then solidified by means of a thermal polymerization process. The dielectric layers (17,18) are subjected to a etch-back treatment and to a subsequent thermal annealing treatment.

摘要翻译： 的位线的多个（6）彼此隔离由多层介电结构提供一种平面结构走上选择性设置的导电层的哪个可被沉积。 在本专利申请中提出的方法沉积在介电结构采用旋涂在第一电介质绝缘层（17），然后通过热聚合工艺来固化SOG的类型的高平坦化介电层（18）。 介电层（17,18）经受一个回蚀刻处理和随后的热退火处理。

公开(公告)号：EP0851485A1

公开(公告)日：1998-07-01

申请号：EP96830649.8

申请日：1996-12-24

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Camerlenghi, Emilio ,  Colabella, Elio ,  Pividori, Luca ,  Rebora, Adriana, SGS-Thomson Microelectronics Srl

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/3213 ,  H01L21/76838

摘要： Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions made up of a first conducting layer (4), an intermediate dielectric layer (5) and a second conducting layer (6) with said regions being insulated from each other by insulation regions (7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips implemented by means of:

a vertical profile etching for complete removal from the unprotected areas of the first conducting layer (11,12), of the second conducting layer (6) and of the intermediate dielectric layer (5) respectively, and
a following isotropic etching of the first conducting layer (4).

摘要翻译： 自对准蚀刻工艺，用于在沉积在由半导体衬底（1）开始的平坦化架构（9）上沉积的第一导电层（11,12）中提供多个相互平行的字线，其上设置有多个有源元件 沿着单独的平行线延伸，例如 存储单元位线（13），并且包括由第一导电层（4），中间介电层（5）和第二导电层（6）构成的栅极区域，所述区域由绝缘区域（7）彼此绝缘 ，8）以形成所述架构（9），其中所述字线由光刻地通过保护条定义，所述保护条通过以下方式实现：垂直轮廓刻蚀，用于从第一导电层（11,12）的未保护区域完全去除第二导电层 导电层（6）和中间介电层（5），以及对第一导电层（4）进行以下各向同性蚀刻。

公开(公告)号：EP0851484A1

公开(公告)日：1998-07-01

申请号：EP96830648.0

申请日：1996-12-24

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Colabella, Elio ,  Pividori, Luca ,  Rebora, Adriana, SGS-Thomson Microelectronics Srl

IPC分类号： H01L21/8247

CPC分类号： H01L27/11521 ,  H01L21/3213 ,  H01L21/76838

摘要： The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells.
The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions formed by a first conducting layer (4), a dielectric interpoly layer (5) and a second conducting layer (6) with said regions being insulated from each other by dielectric insulation films(7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips is implemented by means of:

a vertical profile etching for complete removal from the unprotected areas respectively of the first conducting layer (11,12), of the second conducting layer (6) of the gate region,
a successive etching of the dielectric interpoly layer (5) accompanied by a considerable erosion of the dielectric film (8) of the insulation region so as to totally uncover the first conducting layer (4), and
a concluding etching of the first conducting layer (4).

摘要翻译： 所提出的方法允许使用能够去除相邻存储器单元之间的这些寄生电触点的自对准蚀刻来提供电子存储器件的矩阵形貌。 自对准蚀刻工艺被提出用于在沉积在由半导体衬底（1）开始的半导体衬底（1）上获得的平坦化架构（9）上的第一导电层（11,12）中提供多个相互平行的字线， 活动元件沿独立的平行线延伸，例如 存储单元位线（13）并且包括由第一导电层（4），介电层间层（5）和第二导电层（6）形成的栅极区域，所述区域通过介电绝缘膜（7）彼此绝缘 ，8）以形成所述架构（9），其中用保护条光刻地限定的所述字线通过以下方式实现：垂直轮廓刻蚀，用于从第一导电层（11,12）的未保护区域完全去除， 所述栅极区域的第二导电层（6）对所述绝缘区域的介电膜（8）的相当大的侵蚀伴随着所述介电层间层（5）的连续蚀刻，从而完全露出所述第一导电层（4） ）和第一导电层（4）的总结蚀刻。

公开(公告)号：EP0851426A3

公开(公告)日：1999-11-24

申请号：EP97830238.8

申请日：1997-05-23

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Pividori, Luca

IPC分类号： G11C7/00 ,  G11C16/04 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0491 ,  H01L27/115

摘要： An electronic memory device organized into sections which are in turn divided into blocks (1) formed of cells (3) and their associated decoding and addressing circuits (2), the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions (4) which are interconnected by parallel continuous conduction lines referred to as the bit lines (7) . In the present invention, at least one interruption is provided in each bit line (7) near a contact region (4) by inserting a controlled switch (9) which functions as a block selector (8). Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches (9) of the cascade connected blocks (1). Also provided is a method of implementing the memory block (1), as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell (3) is identified by a continuous bit line (7) enabled by at least one block selector (8), by a broken bit line or 'segment' (13) connected to the continuous one (7) through an address device (2), and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type fo conductivity.

公开(公告)号：EP0851479A1

公开(公告)日：1998-07-01

申请号：EP96830644.9

申请日：1996-12-24

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Sonego, Patrizia ,  Colabella, Elio ,  Bacchetta, Maurizio ,  Pividori, Luca

IPC分类号： H01L21/768 ,  H01L21/31 ,  H01L21/3105 ,  H01L21/316

CPC分类号： H01L21/31051 ,  H01L21/31053 ,  H01L21/76801 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76837

摘要： A method of depositing a dielectric ply structure to optimize the planarity of electronic devices which include a plurality of active elements having gate regions laid across the substrate as discrete parallel lines, such as the bit lines of memory cells.
The proposed solution in accordance with the principles of this invention allows the plurality of bit lines to be isolated from one another by a suitable dielectric ply structure to provide a planar architecture onto which an optional conductive layer may be deposited.
A plurality of word lines can be formed from the conductive layer by conventional photolithographic and dry-wet etching processes.
These lines intersect the plurality of bit lines to define a plurality of EPROM cells organized into a matrix-like topography.
The resulting planarization is adequate to avoid the typical shortcomings of the prior art, such as the lack of electrical continuity in the word lines or their excessively high electrical resistance from slenderized portions in the conductive sections due to poor planarity of the surfaces whereon the conductive layer is deposited.

摘要翻译： 沉积电介质层结构的方法，以优化该系统包括具有横跨基材铺设为离散线并联栅极区域有源元件的多个电子装置的平面：存储器单元的位线，如。 在雅舞蹈提出的解决方案与本发明的原理允许位线多元性到彼此通过一个合适的电介质帘布层结构来分离，以提供一个平面架构走上选择性设置的导电层的哪个可被沉积。 的字线的多个可以通过常规的光刻和干 - 湿蚀刻工艺，导电层来形成。 这些线相交的位线的多元化，以限定组织成矩阵状地形EPROM单元的复数。 将所得的平坦化是足够的，以避免现有技术,:的典型的短缺憾，例如在字线的缺乏电连续性或从导电部分由于表面的平坦性差，其上在导电层拉伸细化部分及其过高电阻 沉积。

公开(公告)号：EP0851426A2

公开(公告)日：1998-07-01

申请号：EP97830238.8

申请日：1997-05-23

申请人： SGS-THOMSON MICROELECTRONICS s.r.l.

发明人： Camerlenghi, Emilio ,  Cappelletti, Paolo ,  Pividori, Luca

IPC分类号： G11C7/00 ,  G11C16/04 ,  H01L21/8247

CPC分类号： H01L27/11521 ,  G11C7/18 ,  G11C8/12 ,  G11C16/0491 ,  H01L27/115

摘要： An electronic memory device organized into sections which are in turn divided into blocks (1) formed of cells (3) and their associated decoding and addressing circuits (2), the cells being connected in a predetermined circuit configuration and each block being included between two opposite contact regions (4) which are interconnected by parallel continuous conduction lines referred to as the bit lines (7) . In the present invention, at least one interruption is provided in each bit line (7) near a contact region (4) by inserting a controlled switch (9) which functions as a block selector (8).
Advantageously, the proposed solution allows each block to be isolated individually by enabling or disabling as appropriate the switches (9) of the cascade connected blocks (1).
Also provided is a method of implementing the memory block (1), as organized into a matrix-like configuration, individually selectable from a plurality of blocks embedded in a memory device, wherein each memory cell (3) is identified by a continuous bit line (7) enabled by at least one block selector (8), by a broken bit line or 'segment' (13) connected to the continuous one (7) through an address device (2), and by a word line orthogonal to the direction of the bit lines, and formed on a substrate having a first type fo conductivity.

摘要翻译： 组织成其又分为块部分电子存储装置（1）形成的单元（3）和它们的相关联的解码和处理电路（2），被包括两者之间被连接在规定的电路配置中的细胞，并且每个块 哪些是由被称为位线（7）平行的连续导线互连相对的接触区（4）。 （9）其功能是作为一个选择器块（8）在本发明中，至少一个中断，在每个位线（7）的接触区（4）附近通过将受控开关提供。 有利的是，提出的解决方案允许每个块单独地通过启用或禁用适当地隔离开关（9）的级联连接的模块（1）。 这样提供了一种实施存储块（1）中，作为组织成矩阵状的结构中，从嵌入在存储装置中的块的多个可单独选择，worin每个存储单元（3）的鉴定通过连续位线的方法 （7）通过至少一个块选择器（8）使能时，通过在地址装置（2）连接到连续一个（7）一个破碎位线或“段”（13），和由字线正交的 位线的方向，并且形成在具有第一导电类型FO一个基材。