Method and device for suppressing parasitic effects in a junction-insulated integrated circuit
    1.
    发明公开
    Method and device for suppressing parasitic effects in a junction-insulated integrated circuit 失效
    装置和方法,用于抑制在集成电路中具有的pn绝缘区的寄生效应

    公开(公告)号:EP0847089A1

    公开(公告)日:1998-06-10

    申请号:EP96830614.2

    申请日:1996-12-09

    IPC分类号: H01L27/088 H01L27/02

    CPC分类号: H01L27/0248 H01L27/088

    摘要: The method described is applied to an integrated circuit formed on a substrate (10) of p-type material having at least one region (11) of n-type material with junction insulation, first electrical contact means (20,21) on the frontal surface of the substrate, second electrical contact means (14,14') on the n-type region (11) and third electrical contact means (8) on the back of the substrate connected to a reference (ground) terminal of the integrated circuit. To avoid current in the substrate due to the conduction of parasitic bipolar transistors in certain operating conditions of the integrated circuit, the method provides for monitoring the potential of the second contact means (14,14') to detect if this potential departs from the (ground) potential of the reference terminal by an amount greater than a predetermined threshold value. If this occurs the first contact means (20,21) are taken to the potential of the second contact means (14,14'), otherwise they are held at the (ground)potential of the reference terminal. A device and an integrated circuit which utilise the method are also described.

    摘要翻译: 所描述的方法被施加到与形成于具有n型材料中的至少一个区域(11),且结绝缘,第一电接触装置(20,21)上的头的p型材料的基片(10)的集成电路 在n型区域(11)和第三电接触装置的基板,第二电接触器件(14,14“)的表面(8)上连接到所述集成电路的基准(接地)端子的基板的背面 , 为了避免在基片的电流由于寄生双极晶体管的集成电路中,所述方法提供了用于监测所述第二接触装置(14,14“)的电势的某些操作条件的导通来检测,如果该电势从出发( 地)通过在量高于预定阈值的参考端子的电势。 如果发生此第一接触装置(20,21)被带到第二接触装置(14,14“)的电位,否则,这些都在参考端子的(接地)电势保持。 因此,一个装置和集成电路,其利用该方法进行了描述。