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公开(公告)号：EP4434093A1
公开(公告)日：2024-09-25
申请号：EP22809115.3
申请日：2022-10-25
IPC分类号： H01L29/775 , H01L27/088 , H01L21/336 , H01L29/06 , H01L29/51 , H01L21/8234 , B82Y10/00
CPC分类号： B82Y10/00 , H01L29/66439 , H01L29/775 , H01L29/0673 , H01L27/088 , H01L21/823462 , H01L29/513 , H01L29/517 , H01L21/823412
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公开(公告)号：EP4383341A3
公开(公告)日：2024-07-24
申请号：EP23192937.3
申请日：2023-08-23
发明人： SHIN, Dong Suk , KIM, Jung Taek , YU, Hyun-Kwan , KIM, Seok Hoon , PARK, Pan Kwi , JEONG, Seo Jin , CHO, Nam Kyu
IPC分类号： H01L29/06 , H01L29/08 , H01L29/161 , H01L29/165 , H01L29/417 , H01L29/423 , H01L29/66 , H01L29/775 , H01L29/201 , B82Y10/00 , H01L29/78 , H01L27/088
CPC分类号： B82Y10/00 , H01L29/0673 , H01L29/66439 , H01L29/775 , H01L29/0847 , H01L29/161 , H01L29/165 , H01L29/66545 , H01L29/41766 , H01L29/7848 , H01L29/42392 , H01L29/201 , H01L27/088 , H01L29/66553 , H01L29/6656 , H01L29/78696
摘要： There is provided a semiconductor device, preferably a nanosheet field-effect transistor, capable of improving performance and reliability of an element. The semiconductor device includes an active pattern (NS1) extending in a first direction, (D1) and a plurality of gate structures (INT_GS1) spaced apart from each other in the first direction on the active pattern. Each gate structure comprises a gate electrode (120) extending in a second direction and a gate spacer (GS1, 140) on a sidewall of the gate electrode and a source/drain pattern (150, 151, 152) disposed between adjacent gate structures. The source/drain structure comprises a semiconductor liner layer (151) and a semiconductor filling layer (152) on the semiconductor liner layer, wherein the semiconductor liner layer and the semiconductor filling layer are formed of silicon-germanium. The semiconductor filling layer comprises an upper portion (152UP) protruding in a third direction beyond an upper surface of the active pattern (NS1). A maximum width of the upper portion of the semiconductor filling layer in the first direction is greater than a width of the semiconductor filling layer in the first direction at the vertical position of the upper surface of the active pattern (NS1). Furthermore, in a plan view (Fig. 5), the inner surface of the semiconductor liner layer comprises a concave region.
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公开(公告)号：EP4391040A1
公开(公告)日：2024-06-26
申请号：EP22214440.4
申请日：2022-12-19
申请人： IMEC VZW
发明人： GUPTA, Anshul , MERTENS, Hans
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786 , H01L23/528 , H01L21/74 , H01L23/535
CPC分类号： H01L21/823475 , H01L21/823481 , H01L27/088 , H01L29/775 , H01L29/0673 , H01L29/66439 , H01L29/78696 , H01L21/743 , H01L23/535 , H01L23/5286
摘要： The disclosure relates to a method for forming an integrated circuit device, comprising:
forming a forksheet device (102) on a frontside of a substrate (101), the forksheet device comprising a first (102a) and a second transistor (102b) separated by a vertically oriented dielectric wall (114), wherein the forksheet device is formed over a base portion of the substrate and the dielectric wall extends into the base portion;
subsequent to forming the forksheet device, thinning the substrate from a backside of the substrate;
subsequent to the thinning, forming a first trench underneath the first transistor and a second trench underneath the second transistor by etching the base portion from the backside, the first and second trenches being separated by the dielectric wall; and
forming a first backside wiring line(130a) in the first trench and a second backside wiring line (130b) in the second trench
The disclosure further relates to a semiconductor device comprising a forksheet device and first and second backside wiring lines.-
公开(公告)号：EP4376066A1
公开(公告)日：2024-05-29
申请号：EP23204015.4
申请日：2023-10-17
发明人： YU, Changyeon , KWAK, Pansuk
IPC分类号： H01L21/8234 , H01L27/02 , H01L27/088
CPC分类号： H01L27/088 , H01L21/823475 , H01L21/823493 , H01L21/823462 , H01L27/0207
摘要： A semiconductor device includes a substrate (PSUB), a P-well region (PW), a first N-type metal oxide semiconductor (NMOS) transistor (NM1) provided in the P-well region, a second NMOS transistor (NM2) provided on the substrate, and a common body bias region (JCB) provided between the first NMOS transistor and the second NMOS transistor and contacting both the P-well region and the substrate.
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公开(公告)号：EP4374422A1
公开(公告)日：2024-05-29
申请号：EP22764920.9
申请日：2022-07-21
申请人： Synopsys, Inc.
发明人： MOROZ, Victor , LEFFERTS, Robert B. , LIN, Xi-Wei , CHOI, Munkang
IPC分类号： H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/775 , H01L29/786
CPC分类号： H01L27/088 , H01L29/775 , H01L29/0673 , H01L29/78696 , H01L29/66439 , H01L21/823462 , B82Y10/00 , H01L29/42392 , H01L29/513
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6.发明公开
公开(公告)号：EP4358138A1
公开(公告)日：2024-04-24
申请号：EP23203815.8
申请日：2023-10-16
发明人： PARK, Keumseok , BAEK, Jaejik , PARK, Sooyoung , SEO, Kang-Ill
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/775 , H01L21/822 , H01L27/06 , H01L29/06
CPC分类号： H01L27/0688 , H01L21/8221 , H01L27/088 , H01L21/823418 , H01L29/775 , H01L29/0673 , B82Y10/00 , H01L29/66439 , H01L29/41725 , H01L29/42392
摘要： Integrated circuit devices and methods of forming the same are provided. An integrated circuit device may include a substrate (122) and a transistor stack on the substrate (122), the transistor stack including a first transistor and a second transistor on the first transistor. The first transistor may be between the substrate (122) and the second transistor and the first transistor may include first and second source/drain regions (110, 112), a first channel region (102) between the first and second source/drain regions (110, 112), and a first gate structure (106) on the first channel region (102). A lower surface of the first source/drain region (110) may be higher than a lower surface of the first gate structure (106) relative to the substrate (122).
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公开(公告)号：EP3051587B1
公开(公告)日：2018-12-12
申请号：EP16159240.7
申请日：2001-09-14
发明人： WEBER, David , YUE, Patrick , SU, David
CPC分类号： H01L24/06 , H01L23/66 , H01L24/48 , H01L24/49 , H01L27/088 , H01L2223/6644 , H01L2224/05554 , H01L2224/48247 , H01L2224/48257 , H01L2224/4911 , H01L2224/49171 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01023 , H01L2924/01031 , H01L2924/01051 , H01L2924/01052 , H01L2924/10329 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19042 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H01L2924/3025 , H03F1/223 , H03F3/24 , H03F3/45188 , H03F2200/06 , H03F2203/45638 , H03F2203/45652 , H04B2001/0408 , Y10S977/724 , H01L2924/00 , H01L2224/45099
摘要： The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.
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公开(公告)号：EP3349358A1
公开(公告)日：2018-07-18
申请号：EP16844472.7
申请日：2016-09-09
发明人： TAMURA Ryosuke , SUGIMOTO Kaoru , KAYA Syusuke
IPC分类号： H03K17/16 , H01L21/8232 , H01L21/8234 , H01L27/06 , H01L27/088 , H03K17/687
CPC分类号： H01L23/645 , H01L21/02378 , H01L21/02381 , H01L21/0254 , H01L21/8232 , H01L21/8234 , H01L21/8258 , H01L23/66 , H01L24/48 , H01L27/0255 , H01L27/0288 , H01L27/06 , H01L27/0605 , H01L27/088 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/7787 , H01L2223/6627 , H01L2224/48245 , H01L2924/19032 , H01P3/081 , H03K17/08116 , H03K17/16 , H03K17/168 , H03K17/687
摘要： There is provided a power device capable of easily designing a switching circuit that takes measures against high frequency noise while maintaining a switching speed without change.
The power device (10, 10A to 10D) includes a normally-on type first transistor (12), a normally-off type second transistor (14), and an electric path (16) that forms a cascode connection between the first transistor (12) and the second transistor (14), and contains an inductance component (32).-
公开(公告)号：EP3338308A1
公开(公告)日：2018-06-27
申请号：EP16757402.9
申请日：2016-08-09
申请人： Raytheon Company
IPC分类号： H01L29/417 , H01L29/423 , H01L23/66 , H01L29/812
CPC分类号： H01L27/088 , H01L23/481 , H01L23/66 , H01L29/0696 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/4238 , H01L29/812 , H01L2223/6622 , H01L2223/6627 , H01L2224/48091 , H01L2924/00014
摘要： A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.
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10.发明公开
公开(公告)号：EP3338307A1
公开(公告)日：2018-06-27
申请号：EP16754592.0
申请日：2016-08-09
申请人： Raytheon Company
IPC分类号： H01L29/417 , H01L29/423 , H01L29/812
CPC分类号： H01L27/088 , H01L29/0696 , H01L29/2003 , H01L29/41758 , H01L29/42316 , H01L29/4238 , H01L29/812
摘要： A Field Effect Transistor (FET) having: a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads; a gate contact connected to the gate electrodes of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed on a surface in a two-dimensional array.
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