公开(公告)号：EP0776574B1

公开(公告)日：1999-02-10

申请号：EP95928442.3

申请日：1995-08-18

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： PRANGE, Stefan ,  GEIB, Heribert ,  HAMMER, Bernard ,  PANDEL, Jürgen

IPC分类号： H04N7/46

CPC分类号： H04N19/577 ,  H04N19/423 ,  H04N19/426 ,  H04N19/61

摘要： For bidirectional motion-compensated interpolation in the decoding of compressed video sequences, the invention proposes that only one of the two reference images is completely decoded. From the other reference image, only those areas of the image are decoded which overlap with the area being processed of the interpolated image, allowing for the displacement related to motion compensation.

公开(公告)号：EP0549623B1

公开(公告)日：1994-11-30

申请号：EP91915681.0

申请日：1991-09-02

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： GEIB, Heribert

IPC分类号： G11C11/409 ,  G11C7/06

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： The invention relates to a dynamic semiconductor memory having at least one word line block (WLB) consisting of a plurality of bit line blocks (TB, TB', ...) and, per bit line block, a local SAN driver (LTN) and possibly also a local SAP driver (LTP) to control the read amplifiers (LV) belonging to this bit line block (TB) in order to prevent undesirable voltage drops on long driver lines. In order to obtain optimised control, it has multi-stage local SAN drivers (LTN) or SAP drivers (LTP) whose transistors usually have different channel widths.

公开(公告)号：EP0627117B1

公开(公告)日：1995-09-27

申请号：EP93902065.7

申请日：1993-02-01

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： GEIB, Heribert

IPC分类号： G11C11/408

CPC分类号： G11C11/4082

摘要： The invention calls for a store. The invention also calls for a first MOS transistor (T1) which, when a first control signal (S1) is applied, switches an input signal corresponding to the bit to the store input. The store has means for bringing, in dependence on the input-signal level, an output signal at the store output to a pre-determined potential. The circuit is particularly suitable for use in the construction of an address buffer store (address latch) for DRAMs, in particular 16M-generation DRAMs.

公开(公告)号：EP1020024A1

公开(公告)日：2000-07-19

申请号：EP98952553.0

申请日：1998-09-09

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： PRANGE, Stefan ,  GEIB, Heribert ,  DE MAN, Erik

IPC分类号： H03D3/00 ,  H03D1/22 ,  H03D7/16

CPC分类号： H04L27/3854 ,  H03D1/2245 ,  H03D3/007 ,  H04N5/205 ,  H04N5/455

摘要： The invention relates to a filter arrangement for a demodulated quadrature amplitude modulated (QAM) signal comprising a first channel (17I) for a cosinusoidale demodulated component of the QAM signal, a second channel (17Q) for a sinusoidal demodulated component of the QAM signal, a filter circuit (10', 10'') which receives two said signal components and has a transmission function for each signal component. The transmission function is comprised of terms which are in-phase with said signal component and out-of-phase with said signal component by π/2 and/or -π/2. The filter circuit is comprised of a cross arm (9) for tapping the out-of-phase terms of the transmission function corresponding to the portions of the signal from the other respective channel. In order to produce a filter arrangement requiring less circuitry and to integrate a semiconductor substrate onto a smaller surface, an inventive circuit configuration (19, 21; 19, 23) is provided. In a first mode, said circuit configuration connects the input of the cross arm (9) to the first channel (17I) and the output thereof to the second channel (17Q). In a second mode, said circuit configuration connects the input of the cross arm (9) to the second channel (17Q) and the output thereof to the first channel (17I). In addition, a suited slope detector is specially provided for use with said filtering arrangement.

公开(公告)号：EP0627117A1

公开(公告)日：1994-12-07

申请号：EP93902065.0

申请日：1993-02-01

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： GEIB, Heribert

IPC分类号： G11C11

CPC分类号： G11C11/4082

摘要： L'invention concerne une mémoire. Il est prévu un premier transistor MOS (T1) qui commute en présence d'un premier signal de commande (S1) un signal d'entrée correspondant au bit sur l'entrée de la mémoire. La mémoire est équipée de dispositifs grâce auxquels un signal de sortie à la sortie de la mémoire est amené à un potentiel déterminé en fonction du niveau du signal d'entrée. Le circuit convient en particulier pour la réalisation d'une mémoire intermédiaire d'adresses (bascule d'adresses) pour des mémoires RAM dynamiques, en particulier des mémoires RAM dynamiques de la génération 16 M.

公开(公告)号：EP0836785A1

公开(公告)日：1998-04-22

申请号：EP96916011.0

申请日：1996-06-13

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： GEIB, Heribert ,  PRANGE, Stefan

IPC分类号： H04N7

CPC分类号： H04N19/577 ,  H04N19/423 ,  H04N19/428 ,  H04N19/61

摘要： A process is disclosed for coding and decoding a video data stream. When the video data stream is coded or decoded, only one image that is required to reconstruct interpolated images is stored in a completely decompressed form. The part of a second basic image (G2) required in its decompressed form to construct or reconstruct an interpolated image is temporarily decompressed. In another embodiment, a first basic image (G1) and the second basic image (G2) are stored in a compressed form and only those areas that are required to construct or reconstruct an interpolated image are temporarily decompressed. Memory requirements are thus considerably reduced in comparison with known processes.

公开(公告)号：EP0549623A1

公开(公告)日：1993-07-07

申请号：EP91915681.0

申请日：1991-09-02

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： GEIB, Heribert

IPC分类号： G11C11

CPC分类号： G11C11/4097 ,  G11C11/4091

摘要： L'invention concerne une mémoire dynamique à semi-conducteurs comportant au moins un bloc de lignes de mots (WLB), chaque bloc de lignes de mots étant constitué d'un grand nombre de blocs de lignes de bits (TB, TB' ...), mémoire qui possède, pour chaque bloc de lignes de bits, un circuit d'attaque local SAN (LTN) et également, le cas échéant, un circuit d'attaque local SAP (LTP) pour commander les amplificateurs de lecture (LV) appartenant à ce bloc de lignes de bits (TB), pour éviter des chutes de tension perturbatrices sur les lignes de circuits d'attaque de grande longueur, et qui possède également, pour obtenir une fonction de commande optimisée, des circuits d'attaque locaux SAN à plusieurs étages (LTN) ou des circuits d'attaque SAP (LTP), dont les transistors présentent normalement des largeurs de canaux différentes.

公开(公告)号：EP0776574A1

公开(公告)日：1997-06-04

申请号：EP95928442.0

申请日：1995-08-18

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： PRANGE, Stefan ,  GEIB, Heribert ,  HAMMER, Bernard ,  PANDEL, Jürgen

IPC分类号： H04N7

CPC分类号： H04N19/577 ,  H04N19/423 ,  H04N19/426 ,  H04N19/61

摘要： For bidirectional motion-compensated interpolation in the decoding of compressed video sequences, the invention proposes that only one of the two reference images is completely decoded. From the other reference image, only those areas of the image are decoded which overlap with the area being processed of the interpolated image, allowing for the displacement related to motion compensation.

公开(公告)号：EP0549611B1

公开(公告)日：1994-06-15

申请号：EP91915129.0

申请日：1991-09-03

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： RAAB, Wolfgang ,  GEIB, Heribert

IPC分类号： G11C11/409

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： The invention relates of a dynamic semiconductor store which can be divided into word and bit line blocks in which word line blocks consist of a plurality of bit line blocks, has a local SAN driver (LTN) and an acceleration circuit to tune the read amplifier (LV1...LVi) belonging to the bit line block concerned per bit line block, the acceleration circuits of which can be tuned to that, to obtain a low total peak current, only that acceleration circuit is active which belongs to the bit line block whose bit lines are connected to I/O lines (IO, ION). The acceleration circuit consists, for example, only of one driver transistor (NTn+1).

公开(公告)号：EP0549611A1

公开(公告)日：1993-07-07

申请号：EP91915129.0

申请日：1991-09-03

申请人： SIEMENS AKTIENGESELLSCHAFT

发明人： RAAB, Wolfgang ,  GEIB, Heribert

IPC分类号： G11C11

CPC分类号： G11C11/4091 ,  G11C11/4097

摘要： L'invention concerne une mémoire dynamique à semi-conducteurs pouvant être répartie en blocs de lignes de mots et en blocs de lignes de bits, les blocs de lignes de mots étant subdivisés en un grand nombre de blocs de lignes de bits, mémoire qui possède, pour chaque bloc de lignes de bits, un circuit d'attaque de petits réseaux locaux (LTN) et un circuit d'accélération commandant l'amplificateur de lecture (LV1...LVi) du bloc de lignes de bits correspondant et dont les circuits d'accélération peuvent être commandés de telle manière que, pour obtenir un faible courant de crête total, le seul circuit d'accélération qui soit actif soit toujours celui qui appartient au bloc de ligne de bits dont les lignes de bits sont branchées chacune sur des circuits d'entrée/sortie (IO, ION). Le circuit d'accélération n'est constitué, par exemple, que d'un transistor d'attaque (NTn+1).