公开(公告)号：EP0055126B1

公开(公告)日：1986-05-07

申请号：EP81306040.7

申请日：1981-12-22

申请人： SPERRY CORPORATION

发明人： O'Brien, Steven Michael

IPC分类号： G06F5/00

CPC分类号： G06F11/10 ,  G06F5/01

公开(公告)号：EP0055126A3

公开(公告)日：1983-08-03

申请号：EP81306040

申请日：1981-12-22

申请人： SPERRY CORPORATION

发明人： O'Brien, Steven Michael

IPC分类号： G06F05/00

CPC分类号： G06F11/10 ,  G06F5/01

摘要： Byte shifting apparatus for high speed bus architecture data processing systems comprises a plurality of byte shifters (14, 15, 16, 17), one for each byte, each with a corresponding number of input ports (e.g. 18, 19, 20, 22) and an output port (18). Data are read from the bus (13) into each byte shifter through one of its input ports selected by shift control means (37) and are returned to the bus through its output port. Fill logic (56) is provided for filling bytes with ones or zeros as required before returning them to the bus. Checking means, not shown in Figure 1, are provided within each byte shifter for checking bit parity, shift error, shift select error, and loading of the buffer register within the shifter with the shifted byte.

公开(公告)号：EP0055126A2

公开(公告)日：1982-06-30

申请号：EP81306040.7

申请日：1981-12-22

申请人： SPERRY CORPORATION

发明人： O'Brien, Steven Michael

IPC分类号： G06F5/00

CPC分类号： G06F11/10 ,  G06F5/01

摘要： Byte shifting apparatus for high speed bus architecture data processing systems comprises a plurality of byte shifters (14, 15, 16, 17), one for each byte, each with a corresponding number of input ports (e.g. 18, 19, 20, 22) and an output port (18). Data are read from the bus (13) into each byte shifter through one of its input ports selected by shift control means (37) and are returned to the bus through its output port. Fill logic (56) is provided for filling bytes with ones or zeros as required before returning them to the bus. Checking means, not shown in Figure 1, are provided within each byte shifter for checking bit parity, shift error, shift select error, and loading of the buffer register within the shifter with the shifted byte.

摘要翻译： 用于高速总线架构数据处理系统的字节移位装置包括多个字节移位器（14,15,16,17），一个用于每个字节，每个具有相应数量的输入端口（例如18,19,20,22） 和输出端口（18）。 数据通过由移位控制装置（37）选择的其中一个输入端口从总线（13）读入每个字节移位器，并通过其输出端口返回总线。 填充逻辑（56）用于在将其返回到总线之前根据需要用1或0填充字节。 在每个字节移位器内提供了检测装置（图1中未示出），用于检查移位器中的位奇偶校验，移位误差，移位选择错误和缓冲寄存器的加载。